US4573146A
Expired / Lapsed
US
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Testing and evaluation of a semiconductor memory containing redundant memory elements
Assignee: STMicroelectronics lnc USA
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Filing: 1982-04-20
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Granted: 1986-02-25
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Expires: 2002-04-20
Abstract
Abstract A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit to determine the implementation of redundant elements in a semiconductor memory. The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit. The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory. An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array. After the memory array has previously received a first data state and the circuit (62) is activated to apply a second data state to the redundant column (63) the memory array is read and each column which produces a second data state is determined to be a redundant column. With knowledge of the column substitution algorithm, it can then be determined which of the redundant columns have been programmed to replace specific original columns. This method can therefore determine the physical configuration of the memory circuit despite the incorporation of redundant elements into the primary memory array.
Inventors
- 👤 Andrew C. Graham
- 👤 Robert J. Proebsting
- 👤 Dennis L. Segers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:27
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/835; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
82 words
A method for evaluating a semiconductor memory fabricated with redundant elements, said semiconductor memory including a memory array having a plurality of memory elements selectable by an address signal wherein the memory array may have one or more of the redundant memory elements implemented therein, the method comprising the steps of: providing a selected functional command mode to said semiconductor memory; and driving said redundant elements to a selected voltage state in response to said command and independent of said address signal.
Claim 2
Independent Claim
82 words
A method for evaluating a semiconductor memory fabricated with redundant elements, said semiconductor memory including a memory array having a plurality of memory elements selectable by an address signal wherein the memory array may have one or more of the redundant memory elements implemented therein, the method comprising the steps of: providing a selected functional command mode to said semiconductor memory; and driving said redundant elements to a selected voltage state in response to said command and independent of said address signal.
Claim 3
Independent Claim
121 words
A method for evaluating a semiconductor memory fabricated with redundant elements, the semiconductor memory having a memory array having a plurality of memory elements which are connectable to transfer data through an input/output line in response to an address signal wherein the memory array may have one or more implemented redundant memory elements therein leaving the rest, if any, of the redundant memory elements as non-implemented redundant memory elements, the method comprising the steps of: receiving a selected functional mode command provided to said semiconductor memory; connecting said implemented and non-implemented redundant memory elements to said input/output line in response to said command; and transmitting a selected voltage state through said input/output line to said implemented and non-implemented redundant memory elements.
Claim 4
Independent Claim
121 words
A method for evaluating a semiconductor memory fabricated with redundant elements, the semiconductor memory having a memory array having a plurality of memory elements which are connectable to transfer data through an input/output line in response to an address signal wherein the memory array may have one or more implemented redundant memory elements therein leaving the rest, if any, of the redundant memory elements as non-implemented redundant memory elements, the method comprising the steps of: receiving a selected functional mode command provided to said semiconductor memory; connecting said implemented and non-implemented redundant memory elements to said input/output line in response to said command; and transmitting a selected voltage state through said input/output line to said implemented and non-implemented redundant memory elements.
Claim 5
Independent Claim
233 words
A method for determining the implementation of redundant column lines in a semiconductor memory which has a memory array having a plurality of column lines wherein the memory array may have redundant column lines incorporated therein, the method comprising the steps of: writing a first data state into a plurality of memory cells connected respectively to the column lines of said memory array; writing a second data state to a memory cell connected to a first addressed one of the column lines of said memory array and writing said second data state to a plurality of memory cells connected respectively to said redundant column lines; reading the ones of said memory cells connected to the column lines of said memory array to determine that the column lines, other than said addressed column line, connected to memory cells which have said second state stored therein are ones of said redundant column lines; writing said first data state to a memory cell connected to a second addressed one of said column lines; writing said second data state to said plurality of memory cells connected respectively to said redundant column lines; and reading the memory cell connected to said second addressed column line to determine that said second addressed column line is one of said redundant column lines if said memory cell connected to said second addressed column line has said second data state stored therein.
Claim 6
Independent Claim
233 words
A method for determining the implementation of redundant column lines in a semiconductor memory which has a memory array having a plurality of column lines wherein the memory array may have redundant column lines incorporated therein, the method comprising the steps of: writing a first data state into a plurality of memory cells connected respectively to the column lines of said memory array; writing a second data state to a memory cell connected to a first addressed one of the column lines of said memory array and writing said second data state to a plurality of memory cells connected respectively to said redundant column lines; reading the ones of said memory cells connected to the column lines of said memory array to determine that the column lines, other than said addressed column line, connected to memory cells which have said second state stored therein are ones of said redundant column lines; writing said first data state to a memory cell connected to a second addressed one of said column lines; writing said second data state to said plurality of memory cells connected respectively to said redundant column lines; and reading the memory cell connected to said second addressed column line to determine that said second addressed column line is one of said redundant column lines if said memory cell connected to said second addressed column line has said second data state stored therein.
Claim 7
Dependent Claim
104 words
A circuit for writing selected data states to redundant memory elements in a semiconductor memory circuit which has a memory array having a plurality of memory elements which transfer data through an input/output line wherein the memory array may have redundant memory elements incorporated therein, said memory circuit having primary address decoders for selecting said memory elements in said memory array and redundant address decoders for selecting the redundant memory elements, the circuit comprising: means for receiving a selected functional mode command signal; and means responsive to said command signal for connecting said redundant memory elements to said input/output line for data transfer therethrough.
Claim 8
Dependent Claim
104 words
A circuit for writing selected data states to redundant memory elements in a semiconductor memory circuit which has a memory array having a plurality of memory elements which transfer data through an input/output line wherein the memory array may have redundant memory elements incorporated therein, said memory circuit having primary address decoders for selecting said memory elements in said memory array and redundant address decoders for selecting the redundant memory elements, the circuit comprising: means for receiving a selected functional mode command signal; and means responsive to said command signal for connecting said redundant memory elements to said input/output line for data transfer therethrough.
Claim 9
Dependent Claim
24 words
The circuit recited in claim 4 wherein said means for connecting includes means responsive to said command signal for disabling said redundant address decoders.
Claim 10
Dependent Claim
19 words
The circuit recited in claim 4 including means responsive to said command signal for disabling said primary address decoders.
Claim 11
Dependent Claim
106 words
A circuit for writing selected data states to redundant column lines in a semiconductor memory circuit which has a memory array having a plurality of column lines which are connectable to transfer data through an input/output line wherein the memory array may have redundant column lines incorporated therein, said memory circuit having primary address decoders for selecting said column lines in said memory array and redundant address decoders for the redundant column lines, the circuit comprising: means for receiving a selected functional mode command signal; and means responsive to said command signal for connecting said redundant column lines to said input/output lines for data transfer therethrough.
Claim 12
Dependent Claim
106 words
A circuit for writing selected data states to redundant column lines in a semiconductor memory circuit which has a memory array having a plurality of column lines which are connectable to transfer data through an input/output line wherein the memory array may have redundant column lines incorporated therein, said memory circuit having primary address decoders for selecting said column lines in said memory array and redundant address decoders for the redundant column lines, the circuit comprising: means for receiving a selected functional mode command signal; and means responsive to said command signal for connecting said redundant column lines to said input/output lines for data transfer therethrough.
Claim 13
Dependent Claim
24 words
The circuit recited in claim 7 wherein said means for connecting includes means responsive to said command signal for disabling said redundant address decoders.
Claim 14
Dependent Claim
19 words
The circuit recited in claim 7 including means responsive to said command signal for disabling said primary address decoders.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-24 | 1989-08-26 | 1990-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-24 | 1993-08-26 | 1994-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-24 | 1997-08-26 | 1998-02-25 | $7700.00 | Window Closed / Lapsed |