Semiconductor memory system

Claim 2

A semiconductor memory system of the serial column access type comprising: "n" regular columns, where "n" is a positive integer; "n" column selection gates provided respectively corresponding to said regular columns; regular data lines connected through said column selection gates respectively to said columns; column selection means for serially selecting said column selection gates; a redundant column used for replacing a defective column; a redundant column selection gate provided for said redundant column; redundant data lines connected to said redundant column through said redundant column selection gate; a data input-output drive circuit; defective address detection means for detecting the address of a defective column to select said redundant column; and data line switching means for switching the data line connecting to the data input-output drive circuit from said regular data lines to said redundant data lines, in response to the detection of the address of a defective column.

Claim 3

A semiconductor memory system according to claim 1, in which said column selection means comprises a shift register.

Claim 4

A semiconductor memory system according to claim 2, wherein the column selection means includes "n" column selection circuits respectively corresponding to the "n" column selection gates, and further comprising: start address set-up means for receiving a start address, and for activating a column selection circuit in said column selection means that corresponds to the start address to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit.

Claim 5

A semiconductor memory system according to claim 1, in which said defective address detection means includes an address counter for monitoring the address, a defective address detection circuit for detecting a defective address from an address signal output by the address counter, and a redundant column selection circuit for selecting the redundant column by driving said redundant column selection gate in response to a defective address detection signal output from said defective address detection circuit, thereby to connect said redundant column to said redundant data lines.

Claim 6

A semiconductor memory system according to claim 4, further comprising start address set-up means for receiving a start address and enabling said column selection means and said address counter.

Claim 7

A semiconductor memory system according to claim 4, in which said data line switching means includes a redundant data-line selection circuit for producing a redundant data-line selection signal in response to the defective address detection signal output from said defective address detection circuit, and a data-line switching circuit for disconnecting, in response to the redundant data-line selection signal of said redundant data-line selection circuit, said regular data lines from said input/output drive circuit, and for connecting said redundant data lines to said input/output drive circuit.

Claim 8

A semiconductor memory system according to claim 6, in which said column selection means comprises a shift register.

Claim 9

A semiconductor memory system according to claim 7, wherein the column selection means includes "n" column selection circuits respectively corresponding to the "n" column selection gates, and further comprising: start address set-up means coupled to said column selection means and said address counter, and responsive to receipt of a start address, for setting the start address in said address counter as an initial value, and for activating a column selection circuit in said column selection means that corresponds to the start address to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit.

Claim 10

A semiconductor memory system according to claim 6, wherein the column selection means includes "n" column selection circuits respectively corresponding to the "n" column selection gates, and further comprising: start address set-up means coupled to said column selection means and said address counter, and responsive to receipt of a start address, for setting the start address in said address counter as an initial value, and for activating a column selection circuit in said column selection means that corresponds to the start address to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit.

Claim 11

A semiconductor memory system according to claim 4, in which said column selection means comprises a shift register.

Claim 12

A semiconductor memory system according to claim 10, wherein the column selection means includes "n" column selection circuits respectively corresponding to the "n" column selection gates, and further comprising: start address set-up means coupled to said column selection means and said address counter, and responsive to receipt of a start address, for setting the start address in said address counter as an initial value, and for activating a column selection circuit in said column selection means that corresponds to the start address to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit.

Claim 13

A semiconductor memory system according to claim 4, wherein the column selection means includes "n" column selection circuits respectively corresponding to the "n" column selection gates, and further comprising: start address set-up means coupled to said column selection means and said address counter, and responsive to receipt of a start address, for setting the start address in said address counter as an initial value, and for activating a column selection circuit in said column selection means that corresponds to the start address to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit.

Claim 14

A semiconductor memory system according to claim 1, in which said data line switching means includes a redundant data-line selection circuit for producing a redundant data-line selection signal in response to a defective address detection signal output from said defective address detection means, and a data-line switching circuit for disconnecting, in response to the redundant data-line selection signal of said redundant data-line selection circuit, said regular data lines from said input/output drive circuit, and for connecting said redundant data lines to said input/output drive circuit.

Claim 15

A semiconductor memory system according to claim 13, in which said column selection means comprises a shift register.

Claim 16

A semiconductor memory system according to claim 14, wherein the column selection means includes "n" column selection circuits respectively corresponding to the "n" column selection gates, and further comprising: start address set-up means for receiving a start address, and for activating a column selection circuit in said column selection means that corresponds to the start address to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit.

Claim 17

A semiconductor memory system according to claim 13, wherein the column selection means includes "n" column selection circuits respectively corresponding to the "n" column selection gates, and further comprising: start address set-up means for receiving a start address, and for activating a column selection circuit in said column selection means that corresponds to the start address to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit.

Claim 18

A semiconductor memory system according to claim 1, wherein the column selection means includes "n" column selection circuits respectively corresponding to the "n" column selection gates, and further comprising: start address set-up means for receiving a start address, and for activating a column selection circuit in said column selection means that corresponds to the start address, to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit.

Claim 19

A semiconductor memory system of the serial column access type comprising: "n" regular columns, where "n" is a positive integer; "n" column selection gates respectively provided corresponding to said regular columns; regular data lines connected through said column selection gates respectively to said columns; column selection means for serially selecting said column selection gates, including "n" column selection circuits respectively corresponding to the "n" column selection gates; a redundant column used for replacing a defective column; a redundant column selection gate provided for said redundant column; redundant data lines connected to said redundant column through said redundant column selection gate; a data input/output drive circuit; defective address detection means for detecting the address of a defective column to enable said redundant column selection gate; an address counter for monitoring the address and for outputting an address signal to said defective address detecting means; start address set-up means coupled to said column selection means and said address counter, and responsive to receipt of a start address, for setting the start address in said address counter as an initial value, and for activating a column selection circuit in said column selection means that corresponds to the start address to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit; a redundant column selection circuit for selecting said redundant column in response to a defective address detection signal from said defective address detection means; and data line switching means for switching the data lines connected to said data input/output drive circuit, from said regular data lines to said redundant data lines, in response to the detection of the address of a defective column.

Claim 20

A semiconductor memory system of the serial column access type comprising: "n" regular columns, where "n" is a positive integer; "n" column selection gates respectively provided corresponding to said regular columns; regular data lines connected through said column selection gates respectively to said columns; column selection means for serially selecting said column selection gates, including "n" column selection circuits respectively corresponding to the "n" column selection gates; a redundant column used for replacing a defective column; a redundant column selection gate provided for said redundant column; redundant data lines connected to said redundant column through said redundant column selection gate; a data input/output drive circuit; defective address detection means for detecting the address of a defective column to enable said redundant column selection gate; an address counter for monitoring the address and for outputting an address signal to said defective address detecting means; start address set-up means coupled to said column selection means and said address counter, and responsive to receipt of a start address, for setting the start address in said address counter as an initial value, and for activating a column selection circuit in said column selection means that corresponds to the start address to enable the column selection means to select the column selection gate corresponding to the activated column selection circuit; a redundant column selection circuit for selecting said redundant column in response to a defective address detection signal from said defective address detection means; and data line switching means for switching the data lines connected to said data input/output drive circuit, from said regular data lines to said redundant data lines, in response to the detection of the address of a defective column.

Claim 21

A semiconductor memory system according to claim 18, in which said data line switching means includes a redundant data-line selection circuit for producing a redundant data-line selection signal in response to a defective address detection signal output from said defective address detection means, and a data-line switching circuit for disconnecting, in response to the redundant data-line selection signal of said redundant data-line selection circuit, said regular data lines from the data input/output drive circuit, and for connecting said redundant data lines to said data input/output drive circuit.

Claim 22

A semiconductor memory system according to claim 18, in which said column selection means comprises a shift register.