US5311472A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Redundant decoder circuit
Assignee: Micron Memory Japan Ltd
•
Filing: 1991-09-13
•
Granted: 1994-05-10
•
Expires: 2011-09-13
Abstract
Abstract A redundant decoder circuit includes a restoration circuit for restoring a decoder which activates a redundant memory cell. When the redundant memory cell which should store a predetermined information is disabled, the restoration circuit stops the decoder from supplying the active signal to the disabled memory cell. Therefore, the predetermined information is to be stored in another memory cell instead of the disabled memory cell, so that the redundant memory cell is used effectively.
Inventors
- 👤 Ken Ota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:57
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/787; G11C29/83; G11C29/832
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
100 words
A redundant decoder circuit comprising: means for storing an address to designate a memory cell of a main memory which is disabled; means for generating a first decode signal, when an address signal coincides with said address stored in said storing means; a memory cell of a redundant memory for storing information, when said first decode signal is generated; and means for restoring said generating means to generate a second decode signal which is an inverted signal of said first decode signal, said restoring means being activated at a time when said memory cell of said redundant memory is disabled.
Claim 2
Dependent Claim
100 words
A redundant decoder circuit comprising: means for storing an address to designate a memory cell of a main memory which is disabled; means for generating a first decode signal, when an address signal coincides with said address stored in said storing means; a memory cell of a redundant memory for storing information, when said first decode signal is generated; and means for restoring said generating means to generate a second decode signal which is an inverted signal of said first decode signal, said restoring means being activated at a time when said memory cell of said redundant memory is disabled.
Claim 3
Dependent Claim
36 words
A redundant decoder circuit, according to claim 1, wherein: said storing means, comprises: a plurality of fuses, some of which are cut in accordance with said address to designate said memory cell of said main memory.
Claim 4
Dependent Claim
62 words
A redundant decoder circuit, according to claim 2, wherein: said storing means, comprises: a fuse connected to a fixed potential determined by one of a power supply voltage and a ground level; and a transistor for supplying said generating means with said fixed potential signal, when said fuse is cut, said second decode signal being generated in accordance with said fixed potential.
Claim 5
Dependent Claim
87 words
A redundant decoder circuit comprising: a first decoder circuit for generating a first decode signal in accordance with a first address signal, by which a first memory cell of a redundant memory is addressed; a second decoder circuit for generating a second decode signal in accordance with a second address signal, by which a second memory cell of a redundant memory is addressed; and a control circuit for addressing said second memory cell in accordance with said first decode signal, when said first memory cell is disabled.
Claim 6
Dependent Claim
87 words
A redundant decoder circuit comprising: a first decoder circuit for generating a first decode signal in accordance with a first address signal, by which a first memory cell of a redundant memory is addressed; a second decoder circuit for generating a second decode signal in accordance with a second address signal, by which a second memory cell of a redundant memory is addressed; and a control circuit for addressing said second memory cell in accordance with said first decode signal, when said first memory cell is disabled.
Claim 7
Dependent Claim
66 words
A redundant decoder circuit, according to claim 4, wherein: said control circuit, comprises: a fuse which is cut, when said first memory cell is disabled; means for inverting said first decode signal thereby to become non-active state, when said fuse is cut; and means for generating said second decode signal under a state that said second address signal is not generated, when said fuse is cut.
References Cited (Backward Citations)
US5058059A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-09 | 1997-11-08 | 1998-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-09 | 2001-11-08 | 2002-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-09 | 2005-11-08 | 2006-05-10 | $7700.00 | Window Closed / Lapsed |