Very high-density DRAM cell structure and method for fabricating it

Claim 1

A semiconductor structure comprising: (a) a silicon substrate; (b) a plurality of parallel digit lines formed on the substrate and separated from each other by isolation structures, (1) each said digit line comprising an N + dopant; (2) each said isolation structure comprising a trench filled with a dielectric, a bottom of said trench being implanted with a P-type channel stop, (3) each said digit line including at least one step-shaped sidewall formed adjacent said trench, at least a portion of said at least one sidewall being covered by a refractory material comprising tungsten, cobalt, titanium, or tantalum; (c) a silicon epitaxial layer formed on said plurality of digit lines, said epitaxial layer being referred to as a word line and comprising: (1) a region above said digit line that comprises a P - dopant at a concentration in the range of 10 15 atoms/cc to 10 16 atoms/cc, referred to as a P - region; (2) a storage node comprising a region of N - dopant formed into an uppermost surface of said epitaxial layer, referred to as an N - region (3) a region above and adjacent said digit line that comprises a P + dopant at a concentration from about 10 20 atoms/cc to about 10 21 atoms/cc, referred to as a P + region (d) an insulator region formed on an uppermost surface of said epitaxial layer, said insulator region having an opening to said N - region; (e) a reference gate comprising a reference polysilicon region, said insulator region extending between said reference polysilicon region and said epitaxial layer; and (f) a capacitor formed on said epitaxial layer, said capacitor comprising: (1) a finned first polysilicon region formed on said insulator region and said N - region; (2) a dielectric material formed on said polysilicon region; and (3) a second polysilicon region formed on said dielectric material.