PROM electrically written by solid phase epitaxy

Claim 3

The method of claim 1 wherein the voltage magnitude and duration is selected to determine the cross-sectional dimension of said column.

Claim 4

The method of claim 1 wherein the voltage magnitude is sufficiently large to create a temperature in the amorphous layer in the range of 400 to 1200 degrees centigrade.

Claim 5

The method of claim 1 wherein the solid-phase epitaxial growth is performed until a layer of palladium silicide is formed between the column and said contact.

Claim 6

The method of claim 1 wherein the substrate is of a first conductivity type and said amorphous layer is formed doped with impurities of said first conductivity type.

Claim 7

The method of claim 5 including forming a region in the surface of said substrate of a conductivity type opposite said first conductivity type to separate said substrate and the subsequently formed amorphous layer.

Claim 8

The method of claim 1 wherein the substrate is of a first conductivity type and said amorphous layer is formed doped with impurities of a conductivity opposite said first conductivity type.

Claim 11

The method according to claim 8 wherein said substrate is of a first conductivity type, said amorphous layer is formed doped with impurities of a conductivity type opposite said first conductivity type and said epitaxial growth produces a layer of palladium silicide between the selected contacts and the single crystal columns to form an ohmic contact and said single crystal comumn forms a PN junction with said substrate.

Claim 12

The method according to claim 8 wherein said substrate is a first conductivity type, said amorphous layer is formed doped with impurities of said first conductivity type, and said epitaxial growth produces a layer of palladium silicide between the selected contacts and the single crystal columns to form a Schottky diode.

Claim 13

The method according to claim 8 wherein said substrate is a first conductivity type and said amorphous layer is formed doped with impurities of said first conductivity type, including forming a plurality of regions of second conductivity type opposite said first conductivity type in said substrate, wherein said palladium silicide regions are formed on said second conductivity type regions, and wherein said column, said second conductivity type regions and said substrate forming a bipolar transistor.

Claim 14

A semiconductor structure comprising: a substrate of single crystal silicon; a first layer of palladium silicide on said substrate; a second layer of doped amorphous silicon on said first layer; a third layer of contact material on said second layer; a column of doped single crystal silicon on said substrate surrounded laterally by said first and second layers; and a fourth layer of palladium silicide between said column and said third layer.

Claim 15

A semiconductor structure comprising: a substrate of single crystal silicon; a first layer of palladium silicide on said substrate; a second layer of doped amorphous silicon on said first layer; a third layer of contact material on said second layer; a column of doped single crystal silicon on said substrate surrounded laterally by said first and second layers; and a fourth layer of palladium silicide between said column and said third layer.

Claim 16

The semiconductor structure according to claim 12 wherein said substrate is of a first conductivity type, said column is of a second conductivity type opposite said first conductivity type, and said semiconductor structure is a diode.

Claim 17

The semiconductor structure according to claim 12 wherein said substrate is of a first conductivity type, said column is of said first conductivity type, and said semiconductor structure is a Schottky diode formed by said column and said fourth layer.

Claim 18

The semiconductor structure according to claim 12 including a region of first conductivity type formed in said substrate between said substrate and said first layer and column, and wherein said substrate and said column are of a second conductivity type opposite said first conductivity type and said semiconductor structure is bipolar transistor formed by said substrate, said region and said column.

Claim 19

In a programmable read only memory including a substrate and a plurality of storage locations formed on said substrate having either a first or second logic state, including at least one storage location in each of said logic states; each storage location having a first logic state comprising a first layer of palladium silicide on said substrate, a second layer of amorphous silicon on said first layer, and a third layer of contact material on said second layer; and each storage location having a second logic state comprising a first, second and third layer as each of said storage locations having a first logic state, a column of doped single crystal silicon extending between said substrate and said third layer and laterally surrounded by said first and second layers, and a fourth layer of palladium silicide between said column and said third layer.

Claim 20

In a programmable read only memory including a substrate and a plurality of storage locations formed on said substrate having either a first or second logic state, including at least one storage location in each of said logic states; each storage location having a first logic state comprising a first layer of palladium silicide on said substrate, a second layer of amorphous silicon on said first layer, and a third layer of contact material on said second layer; and each storage location having a second logic state comprising a first, second and third layer as each of said storage locations having a first logic state, a column of doped single crystal silicon extending between said substrate and said third layer and laterally surrounded by said first and second layers, and a fourth layer of palladium silicide between said column and said third layer.

Claim 21

The read only memory according to claim 16 wherein said substrate and said column are of the same conductivity type.

Claim 22

The read only memory according to claim 16 wherein said column has an impurity concentration sufficiently low to form a Schottky barrier with said fourth layer.

Claim 23

The read only memory according to claim 16 wherein said column is of a conductivity type opposite said substrate forming a PN junction therewith.

Claim 24

The read only memory according to claim 16 wherein some of said columns have different cross-sectional areas representing discrete levels of the second logic state.

Claim 27

The method of claim 21 wherein said solid-phase epitaxial growth is performed until a portion of said alloy layer is transferred from its interface with said substrate to an interface between said column and said contact layer.

Claim 28

The method of claim 22 wherein the amorphous layer is doped with impurities, the impurity conductivity type and concentration and the alloy are selected to produce a diode between said contact and said substrate in a programmed storage location.

Claim 29

The method of claim 23 wherein said amorphous material has sufficiently low impurity concentration and said alloy is selected to form Schottky barrier between said alloy and said column.

Claim 30

The method of claim 23 wherein said amorphous material is doped with impurities of a conductivity type opposite the conductivity type of the impurities of said substrate to form a PN junction with the substrate.

Claim 31

The method of claim 21 wherein said semiconductor material is single crystal silicon and said alloy is palladium silicide.

Claim 34

The method of claim 27 wherein the solid-phase epitaxial growth is performed until a layer of said alloy is formed between the column and said contact layer.

Claim 35

The method of claim 27 wherein said amorphous layer is capable of switching between a high resistance and low resistance state before said solid-phase epitaxial growth occurs.

Claim 36

The method of claim 29 wherein said semiconductor is silicon and said alloy is palladium silicide.

Claim 37

The method of claim 27 wherein said amorphous layer is doped with impurities and said column forms a junction barrier between said contact layer and said single crystal layer.

Claim 38

A semiconductor structure comprising: a layer of single crystal semiconductor material; a alloy layer of a metal and said semiconductor material; a doped amorphous layer of said semiconductor material on said alloy layer; a contact layer of contact material on said amorphous layer; a doped single crystal column of said semiconductor material on said single crystal layer surrounded laterally by said alloy and amorphous layers; and a layer of said alloy between said column and said contact layer.

Claim 39

A semiconductor structure comprising: a layer of single crystal semiconductor material; a alloy layer of a metal and said semiconductor material; a doped amorphous layer of said semiconductor material on said alloy layer; a contact layer of contact material on said amorphous layer; a doped single crystal column of said semiconductor material on said single crystal layer surrounded laterally by said alloy and amorphous layers; and a layer of said alloy between said column and said contact layer.

Claim 40

The semiconductor structure of claim 32 wherein said semiconductor material is silicon and said alloy is palladium silicide.

Claim 41

In a programmable read only memory including a substrate of a semiconductor material and a plurality of storage locations formed on said substrate having either a first or second logic state, including at least one storage location in each of said logic states; each storage location having a first logic state comprising a first layer of an alloy of metal and said semiconductor material on said substrate, a second layer of amorphous form of said semiconductor material on said first layer, and a third layer of contact material on said second layer; and each storage location having a second logic state comprising a first, second and third layer as each of said storage locations having a first logic state, a column of doped single crystal form of said semiconductor material extending between said substrate and said third layer and laterally surrounded by said first and second layers, and a fourth layer of said alloy between said column and said third layer.

Claim 42

In a programmable read only memory including a substrate of a semiconductor material and a plurality of storage locations formed on said substrate having either a first or second logic state, including at least one storage location in each of said logic states; each storage location having a first logic state comprising a first layer of an alloy of metal and said semiconductor material on said substrate, a second layer of amorphous form of said semiconductor material on said first layer, and a third layer of contact material on said second layer; and each storage location having a second logic state comprising a first, second and third layer as each of said storage locations having a first logic state, a column of doped single crystal form of said semiconductor material extending between said substrate and said third layer and laterally surrounded by said first and second layers, and a fourth layer of said alloy between said column and said third layer.

Claim 43

The read only memory according to claim 34 wherein some of said columns have different cross-sectional areas representing discrete levels of the second logic state.

Claim 44

The read only memory according to claim 34 wherein said semiconductor material is silicon and said alloy is palladium silicide.