US5740413A — Method and apparatus for providing address breakp…

Claim 1

Independent Claim 157 words

In a computer system, a method for providing single stopping, said method comprising the steps of: storing information to cause a first address breakpoint event to occur on a second instruction that sequentially follows a first instruction in a routine; executing said first instruction; if execution of said first instruction causes flow of execution to branch to a third instruction in said routine, causing a branch breakpoint event; if flow of execution passes to said second instruction, causing said first address breakpoint event; in response to said branch breakpoint event, executing a first debug routine which stores information to cause a second address breakpoint to occur on a fourth instruction in said routine that sequentially follows said third instruction; and in response to said first address breakpoint event, executing a second debug routine which stores information to cause a third address breakpoint to occur on a fifth instruction in said routine that sequentially follows said second instruction.

Claim 2

Dependent Claim 157 words

In a computer system, a method for providing single stopping, said method comprising the steps of: storing information to cause a first address breakpoint event to occur on a second instruction that sequentially follows a first instruction in a routine; executing said first instruction; if execution of said first instruction causes flow of execution to branch to a third instruction in said routine, causing a branch breakpoint event; if flow of execution passes to said second instruction, causing said first address breakpoint event; in response to said branch breakpoint event, executing a first debug routine which stores information to cause a second address breakpoint to occur on a fourth instruction in said routine that sequentially follows said third instruction; and in response to said first address breakpoint event, executing a second debug routine which stores information to cause a third address breakpoint to occur on a fifth instruction in said routine that sequentially follows said second instruction.

Claim 3

Dependent Claim 41 words

The method of claim 1, said step of storing information further including the steps of: storing a first indication in a first state which enables recognition of address breakpoint events; and storing a data identifying an address of said second instruction.

Claim 4

Dependent Claim 173 words

In a computer system having a processor, said processor operable in a first mode and a second mode, said second mode providing access to storage areas and execution of instructions which are not available in said first mode, a method for single stepping, said method comprising: A) enabling recognition of branch breakpoints while said processor is operating in said first mode; B) storing for an address breakpoint event information identifying a second instruction that sequentially follows a first instruction; C) enabling recognition of said address breakpoint event while said processor is operating in said first mode; C) executing said first instruction in said first mode; D) if execution of said first instruction causes flow of execution to branch to a third instruction, causing a branch breakpoint event; E) if flow of execution passes to said second instruction, causing said address breakpoint event; and F) in response to either said branch breakpoint event or said address breakpoint event, storing information to cause another address breakpoint to occur on a subsequent instruction to be executed.

Claim 5

Dependent Claim 173 words

In a computer system having a processor, said processor operable in a first mode and a second mode, said second mode providing access to storage areas and execution of instructions which are not available in said first mode, a method for single stepping, said method comprising: A) enabling recognition of branch breakpoints while said processor is operating in said first mode; B) storing for an address breakpoint event information identifying a second instruction that sequentially follows a first instruction; C) enabling recognition of said address breakpoint event while said processor is operating in said first mode; C) executing said first instruction in said first mode; D) if execution of said first instruction causes flow of execution to branch to a third instruction, causing a branch breakpoint event; E) if flow of execution passes to said second instruction, causing said address breakpoint event; and F) in response to either said branch breakpoint event or said address breakpoint event, storing information to cause another address breakpoint to occur on a subsequent instruction to be executed.

Claim 6

Dependent Claim 58 words

The method of claim 3, the step of enabling recognition of branch breakpoints further includes the steps of A1) storing a first indication indicating branch breakpoints are enabled while said processor is operating in said first mode; and A2) storing a second indication indicating whether branch breakpoints are enabled while said processor is operating in said second mode.

Claim 7

Dependent Claim 64 words

The method of claim 3, the step of enabling recognition of an address breakpoint event further includes the steps of C1) storing a first indication indicating said address breakpoint event is enabled while said processor is operating in said first mode; and C2) storing a second indication indicating whether said address breakpoint event is enabled while said processor is operating in said second mode.

Claim 8

Dependent Claim 57 words

The method of claim 3, said method further comprising the steps of: in response to said branch breakpoint event, causing said processor to switch to said second mode and execute a first debug routine; and in response to said address breakpoint event, causing said processor to switch to said second mode and execute a second debug routine.

Claim 9

Dependent Claim 32 words

The method of claim 3, further comprising the step of: executing one or more debug routines in said second mode in response to said address breakpoint event or said branch breakpoint event.

Claim 10

Dependent Claim 27 words

The method of claim 3, further comprising the step of: disabling recognition of branch breakpoints and address breakpoints while said processor is operating in said second mode.

Claim 11

Independent Claim 101 words

A method of single-stepping a processor which includes an address breakpoint register, the method comprising the computer implemented steps of: A) executing a current instruction; B) if the current instruction is a branch instruction, generating a branch breakpoint event with a branch breakpoint unit, calculating a target address of the branch instruction, and storing the target address into the address breakpoint register; and C) if the current instruction is not a branch instruction, generating an address breakpoint event with an address breakpoint unit and storing into the address breakpoint register an address of a next sequential instruction after the current instruction.

Claim 12

Independent Claim 101 words

A method of single-stepping a processor which includes an address breakpoint register, the method comprising the computer implemented steps of: A) executing a current instruction; B) if the current instruction is a branch instruction, generating a branch breakpoint event with a branch breakpoint unit, calculating a target address of the branch instruction, and storing the target address into the address breakpoint register; and C) if the current instruction is not a branch instruction, generating an address breakpoint event with an address breakpoint unit and storing into the address breakpoint register an address of a next sequential instruction after the current instruction.

Claim 13

Dependent Claim 23 words

The method of claim 9, wherein: the address breakpoint unit causes a breakpoint event upon detection of an instruction at the target address.

Claim 14

Independent Claim 85 words

A method for performing single stepping using branch and address breakpoints, said method comprising the steps of: enabling branch and address breakpoints; recognizing either a branch breakpoint event in response to a first instruction causing a branch or a first address breakpoint event in response to the first instruction not causing the branch; in response to recognizing either the branch breakpoint event or the first address breakpoint event, storing data to cause a second address breakpoint upon execution of the next instruction to be executed.

Claim 15

Independent Claim 85 words

A method for performing single stepping using branch and address breakpoints, said method comprising the steps of: enabling branch and address breakpoints; recognizing either a branch breakpoint event in response to a first instruction causing a branch or a first address breakpoint event in response to the first instruction not causing the branch; in response to recognizing either the branch breakpoint event or the first address breakpoint event, storing data to cause a second address breakpoint upon execution of the next instruction to be executed.

Claim 16

Dependent Claim 80 words

The method of claim 11, wherein said step of storing data includes the steps of: in response to recognizing the branch breakpoint event, storing said data to cause said second address breakpoint upon execution of the target instruction of the branch; and in response to recognizing the address breakpoint event, storing said data to cause said second address breakpoint upon execution of a second instruction that will be executed as a result of said first instruction not causing the branch.

Claim 17

Dependent Claim 39 words

The method of claim 12, wherein: said step of recognizing includes the step of recognizing said first address breakpoint event in response to executing a third instruction that sequentially follows said first instruction and sequentially precedes said second instruction.

Claim 18

Dependent Claim 40 words

The method of claim 11, wherein said step of storing includes the steps of: interrupting execution of a first routine to which said first instruction belongs; executing a second routine to store said data; resuming execution of said first routine.

Claim 19

Independent Claim 70 words

A method for single-stepping a set of instructions in a program, said method comprising the steps of: enabling address breakpoints for said set of instructions; enabling branch breakpoints; and single-stepping said set of instructions by causing a plurality of branch breakpoint and address breakpoint events, wherein one of a branch breakpoint event and an address breakpoint event is generated in response to each executed instruction of said set of instructions.

Claim 20

Independent Claim 70 words

A method for single-stepping a set of instructions in a program, said method comprising the steps of: enabling address breakpoints for said set of instructions; enabling branch breakpoints; and single-stepping said set of instructions by causing a plurality of branch breakpoint and address breakpoint events, wherein one of a branch breakpoint event and an address breakpoint event is generated in response to each executed instruction of said set of instructions.

Claim 21

Dependent Claim 42 words

The method of claim 15 further comprising the step of: in response to each branch or address breakpoint event, storing data to cause a an address breakpoint event upon execution of the next instruction of said set of instructions to be executed.

Claim 22

Dependent Claim 47 words

The method of claim 15, further including the steps of: executing a handler code in response to each of said plurality of branch breakpoint and address breakpoint events in a different mode than a mode in which said each executed instruction of set of instructions is executed.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-04-13	2001-10-13	2002-04-14	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-04-13	2005-10-13	2006-04-14	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-04-13	2009-10-13	2010-04-14	$7700.00	Window Closed / Lapsed

Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping

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