Composite mask process for semiconductor fabrication

Claim 2

A process for fabricating on a substrate material at least one semiconductor device having electrodes and/or isolation regions or contact regions formed by introducing impurities through specific window regions of said substrate material during separate fabrication process stages, the process including the following steps: (a) forming a first layer of silicon dioxide having a first thickness on an upper surface of said semiconductor substrate material, and defining in said layer of silicon dioxide a plurality of window regions exposing window portions of said upper surface, wherein each of said window regions correspond to a respective electrode of said semiconductor device; (b) forming on said exposed window portions of said upper surface a thin layer of silicon dioxide having a second thickness substantially thinner than said first thickness; (c) forming a layer of silicon nitride overlying said first layer of silicon dioxide and said thin layer of silicon dioxide and defining in said layer of silicon nitride openings exposing selected ones of said window regions, said layer of silicon nitride overlying and covering remaining unselected ones of said window regions; (d) removing said thin layer of silicon dioxide to expose said window portion for at least one of said selected ones of said window regions; and (e) during at least one separate fabrication process stage, introducing by diffusion a first impurity through at least a selected one of said window portions exposed in step (d) to form a first isolation region of said semiconductor device; wherein selected openings of said window regions defined in said layer of silicon nitride at step (c) determine window portions through which impurity is diffused in step (e).

Claim 3

The method of claim 1, including the additional step: (f) after formation of said first isolation region growing a second silicon dioxide to cover said selected one of said window portions through which said first impurity is introduced in step (e); wherein said second silicon dioxide so grown contacts lateral portions of said first layer of silicon dioxide formed at step (a).

Claim 4

The method of claim 2, including the additional step of: (g) removing a region of said layer of silicon nitride at least overlying unselected ones of said window region in step (c), wherein a portion of said thin layer of silicon dioxide underlying said unselected window region in step (c) is exposed; (h) removing said thin layer of silicon dioxide exposed in step (g); and (i) during at least one separate fabrication process stage, introducing by diffusion a second impurity through said unselected window region in step (c) to form a collector contact region or plug region.

Claim 5

The method of claim 3, wherein step (g) includes using an oversize mask defining at least one opening, said opening being as large as said unselected window region in step (c).

Claim 6

The method of claim 1, wherein step (a) includes using a single mask and etching to define said plurality of window regions in said first layer of silicon dioxide.

Claim 7

The method of claim 1, wherein said first thickness exceeds said second thickness by a factor of about ten.

Claim 8

The method of claim 1, wherein step (c) includes forming said layer of silicon nitride to cover said plurality of window regions defined in step (a), and then removing regions of said layer of silicon nitride overlying said selected one of said window regions.

Claim 9

The method of claim 1, wherein step (d) includes using an oversize mask defining at least one window opening, said window opening being at least as large as said window regions in said thin layer of silicon dioxide.

Claim 10

The method of claim 1, wherein for each introduction of said first impurity through said exposed window portion, an overlying portion of said layer of silicon nitride is removed.

Claim 11

The method of claim 1, wherein following each introduction of said first impurity, said exposed window portion through which said first impurity is introduced is covered with a second silicon dioxide.

Claim 12

The method of claim 3, wherein said semiconductor device is a bipolar transistor, said first isolation region defines at least a portion of an isolating barrier surrounding a periphery of said bipolar transistor, and wherein said collector contact region or said plug region includes a collector region of said bipolar transistor.

Claim 13

The method of claim 3, further including the steps of: (j) after formation of said first isolation region, growing a second silicon dioxide to cover said selected one of said window portions through which said first impurity is introduced in step (i), wherein said second silicon dioxide so grown contacts lateral portions of said first layer of silicon dioxide formed at step (a); (k) removing a region of said layer of silicon nitride at least overlying unselected one of said window region that was unselected in step (c) or in step (g), wherein a portion of said thin layer of silicon dioxide underlying unselected one of said window region is exposed; (l) removing said thin layer of silicon dioxide exposed in step (k); and (m) during at least one separate fabrication process stage, introducing by diffusion a third impurity through said unselected window region in step (c) or in step (g) to form a third region of said semiconductor device.

Claim 14

The method of claim 1, wherein after removing said thin layer of silicon dioxide, step (d) further includes forming a new thin layer of silicon dioxide having a third thickness thinner than said second thickness, and wherein diffusion in step (e) occurs through said third thickness of said new thin layer of silicon dioxide.

Claim 15

A process for fabricating, on a substrate of first conductivity-type material that includes a buried layer of second conductivity-type material covered by an epitaxial layer of second conductivity-type material, at least one bipolar transistor having regions of said second conductivity formed by introducing impurities through specific window regions of said substrate material during separate fabrication process stages, the process including the following steps: (a) forming a first layer of silicon dioxide having a first thickness on an upper surface of said semiconductor substrate material, and defining in said layer of silicon dioxide at least first, second, and third window regions exposing first, second and third window portions of said upper surface, said first and second window regions overlying an intended isolation region, and said third window region overlying an intended collector contact region; (b) forming on said exposed first, second and third window portions of said upper surface a thin layer of silicon dioxide having a second thickness substantially thinner than said first thickness; (c) using a single mask, forming a layer of silicon nitride overlying said first layer of silicon dioxide and said thin layer of silicon dioxide, and defining in said layer of silicon nitride openings exposing at least said first and second window regions, said layer of silicon nitride overlying and covering remaining unselected of said unselected window regions; (d) removing said thin layer of silicon dioxide to expose said window portions for at least said first and second window regions; (e) during at least one separate fabrication process stage, introducing by diffusion a first conductivity-type impurity through at least said first and second window portions exposed in step (d) to form an isolation region for said bipolar device; wherein openings defined in said layer of silicon nitride at step (c) determine window portions through which impurity is diffused in step (e); (f) after formation of said isolation region, growing a second silicon dioxide to cover said first and second window portions through which said impurity is introduced in step (e); wherein said second silicon dioxide so grown contacts lateral portions of said first layer of silicon dioxide formed at step (a); (g) removing a region of said layer of silicon nitride at least overlying said third window region, said third window region being unselected in step (c), wherein a portion of said thin layer of silicon dioxide underlying said third window region is exposed; (h) removing said thin layer of silicon dioxide exposed in step (g); and (i) during at least one separate fabrication process stage, introducing by diffusion a second conductivity-type impurity through said third window region to form a collector contact region of a collection region for said bipolar transistor.

Claim 16

A process for fabricating, on a substrate of first conductivity-type material that includes a buried layer of second conductivity-type material covered by an epitaxial layer of second conductivity-type material, at least one bipolar transistor having regions of said second conductivity formed by introducing impurities through specific window regions of said substrate material during separate fabrication process stages, the process including the following steps: (a) forming a first layer of silicon dioxide having a first thickness on an upper surface of said semiconductor substrate material, and defining in said layer of silicon dioxide at least first, second, and third window regions exposing first, second and third window portions of said upper surface, said first and second window regions overlying an intended isolation region, and said third window region overlying an intended collector contact region; (b) forming on said exposed first, second and third window portions of said upper surface a thin layer of silicon dioxide having a second thickness substantially thinner than said first thickness; (c) using a single mask, forming a layer of silicon nitride overlying said first layer of silicon dioxide and said thin layer of silicon dioxide, and defining in said layer of silicon nitride openings exposing at least said first and second window regions, said layer of silicon nitride overlying and covering remaining unselected of said unselected window regions; (d) removing said thin layer of silicon dioxide to expose said window portions for at least said first and second window regions; (e) during at least one separate fabrication process stage, introducing by diffusion a first conductivity-type impurity through at least said first and second window portions exposed in step (d) to form an isolation region for said bipolar device; wherein openings defined in said layer of silicon nitride at step (c) determine window portions through which impurity is diffused in step (e); (f) after formation of said isolation region, growing a second silicon dioxide to cover said first and second window portions through which said impurity is introduced in step (e); wherein said second silicon dioxide so grown contacts lateral portions of said first layer of silicon dioxide formed at step (a); (g) removing a region of said layer of silicon nitride at least overlying said third window region, said third window region being unselected in step (c), wherein a portion of said thin layer of silicon dioxide underlying said third window region is exposed; (h) removing said thin layer of silicon dioxide exposed in step (g); and (i) during at least one separate fabrication process stage, introducing by diffusion a second conductivity-type impurity through said third window region to form a collector contact region of a collection region for said bipolar transistor.

Claim 17

The method of claim 14, wherein at least one of step (c), step (d), and step (g) include using an oversize mask defining at least one opening that is sized larger than a said window region underlying said opening.

Claim 18

The method of claim 14, wherein step (c) includes forming said layer of silicon nitride to cover said first, second and third window regions defined in step (a), and then removing regions of said layer of silicon nitride overlying said first and second window regions.

Claim 19

The method of claim 14, wherein for each introduction of said first and second conductivity type impurities through said exposed said window portion, an overlying portion of said layer of silicon nitride is removed.

Claim 20

The method of claim 14, wherein following each introduction of said first and second conductivity type impurities, said exposed window portion through which said first and second conductivity type impurities are introduced is covered with a second silicon dioxide.

Claim 21

The method of claim 14, wherein step (a) includes further defining a fourth window region overlying an intended base region of said bipolar transistor, and further including the steps of: (j) after formation of said collector contact region, growing a third silicon dioxide to cover said third window portion through which said second conductivity type impurity is introduced in step (i), wherein said third silicon dioxide so grown contacts lateral portions of said first layer of silicon dioxide formed at step (a); (k) removing a region of said layer of silicon nitride at least overlying said fourth window region, wherein a portion of said thin layer of silicon dioxide underlying said fourth window region is exposed; (l) removing said thin layer of silicon dioxide exposed in step (k); and (m) during at least one separate fabrication process stage, introducing by diffusion a first conductivity-type impurity through said fourth window region to form a base electrode region of said bipolar transistor.