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US4018627A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for fabricating semiconductor devices utilizing oxide protective layer

Assignee: Signetics Corp
•
Filing: 1975-09-22
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Granted: 1977-04-19
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Expires: 1995-09-22
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Abstract

Abstract Defect formations and unwanted in diffusions caused by residual impurity products is prevented in a semiconductor fabrication method which includes the step of forming a composite mask which simultaneously defines base, collector and diffusion isolation openings. After these openings are defined a thin protective layer of silicon dioxide is grown over the exposed area and remains there throughout the remainder of the doping process which includes the steps of selectively covering areas which are not to be doped with photoresist and thereafter ashering the photoresist to remove it in preparation for the next ion implantation step. The thin protective layer of silicon dioxide protects nonselected areas against residual impurity products formed during removal of the photoresist.

Inventors

  • 👤 Bohumil Polata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 02:19
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D10/00; H10D10/01; H10D10/051; H10P30/21; H10P30/212; H10W; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/068; Y10S148/085; Y10S148/106; Y10S148/151; Y10S438/00; Y10S438/976

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 124 words
A method for fabricating semiconductor devices from a semiconductor body having a planar surface comprising the steps of forming a layer of material to be utilized as a mask on said surface, forming a plurality of openings in the layer of material to expose areas of said surface, thereafter forming a thin protective layer, relative to said mask, over each of said exposed areas and maintaining said thin protective layer throughout the fabrication steps, and thereafter selectively doping the areas defined by said openings by ion implantation and selectively covering said openings so that areas exposed are not doped until the proper time in said sequence, said thin protective layer protecting nonselected areas from residual impurity products formed during removal of said selective covering.
Claim 2
Independent Claim 124 words
A method for fabricating semiconductor devices from a semiconductor body having a planar surface comprising the steps of forming a layer of material to be utilized as a mask on said surface, forming a plurality of openings in the layer of material to expose areas of said surface, thereafter forming a thin protective layer, relative to said mask, over each of said exposed areas and maintaining said thin protective layer throughout the fabrication steps, and thereafter selectively doping the areas defined by said openings by ion implantation and selectively covering said openings so that areas exposed are not doped until the proper time in said sequence, said thin protective layer protecting nonselected areas from residual impurity products formed during removal of said selective covering.
Claim 3
Dependent Claim 30 words
A method as in claim 1 where said thin layer is silicon dioxide and where said selective covering is accomplished by use of a photoresist which is removed by ashering.

References Cited (Backward Citations)

US3551221A Cited
US3542551A Cited
US3560278A Cited
US3793088A Cited
US3928081A Cited
US3928082A Cited
US3925105A Cited
US3933528A Cited
US3920483A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-04-18 1980-10-18 1981-04-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-04-18 1984-10-18 1985-04-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-04-18 1988-10-18 1989-04-19 $7700.00 Window Closed / Lapsed

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