US4717678A
Expired / Lapsed
US
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Method of forming self-aligned P contact
Assignee: International Business Machines Corp
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Filing: 1986-03-07
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Granted: 1988-01-05
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Expires: 2006-03-07
Abstract
Abstract Disclosed is a process for forming self-aligned low resistance ohmic contact to a P doped region (e.g., base of an NPN device) in conjunction with forming similar contact to a (highly) N doped region (e.g., emitter of NPN). After forming a P doped region in an N type monocrystalline silicon body and masking it with an insulator (e.g. dual oxide-nitride) layer, the highly doped N region (hereafter, N+ region) is formed in a portion of the P doped region by selectively opening the insulator layer and introducing N dopant therethrough. This opening also serves as contact opening for the N+ region. contact opening for the P region is formed by selectively etching the insulator layer. The structure is subjected to a low temperature steam oxidation to from an oxide layers in the P contact and N+ contact regions, the oxide in the N+ contact being about 3-5 times thicker than that in the P contact region due to the significantly higher oxidation rate of the N+ region relative to the P doped region. The oxide in the P contact is etched off while retaining a substantial portion of the oxide grown in the N+ contact region. P type dopant is then introduced into the P contact opening to achieve solid solubility limit of the P dopant species in silicon. The oxide remaining in the N+ contact region is removed and contact metallurgy is established with all contacts.
Inventors
- 👤 George R. Goth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:56
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10P; H10P76/00; H10P76/40; Y; Y10; Y10S; Y10S438/00; Y10S438/911; Y10S438/981
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
181 words
A method for forming low resistance ohmic contacts to doped regions in a semiconductor substrate comprising: providing a semiconductor substrate having at least one region of a first conductivity type and a second region of a second conductivity type on a surface thereof; forming an insulator layer on said substrate surface; forming contact openings in said insulator corresponding to said first and second conductivity type regions; forming an insulator in said openings, by thermal oxidation the insulator in said opening corresponding to said second conductivity type region being 3-5 times thicker than that in said opening corresponding to said first conductivity type region; removing said insulator in said opening corresponding to said first conductivity type region while maintaining substantially said insulator in said opening corresponding to said second conductivity type region; introducing first conductivity type dopant into said first conductivity type region through said corresponding contact opening to reduce contact resistance; removing said insulator in said contact opening to said second conductivity type region; and forming ohmic contacts to said first and second conductivity type regions via said respective contact openings.
Claim 2
Independent Claim
181 words
A method for forming low resistance ohmic contacts to doped regions in a semiconductor substrate comprising: providing a semiconductor substrate having at least one region of a first conductivity type and a second region of a second conductivity type on a surface thereof; forming an insulator layer on said substrate surface; forming contact openings in said insulator corresponding to said first and second conductivity type regions; forming an insulator in said openings, by thermal oxidation the insulator in said opening corresponding to said second conductivity type region being 3-5 times thicker than that in said opening corresponding to said first conductivity type region; removing said insulator in said opening corresponding to said first conductivity type region while maintaining substantially said insulator in said opening corresponding to said second conductivity type region; introducing first conductivity type dopant into said first conductivity type region through said corresponding contact opening to reduce contact resistance; removing said insulator in said contact opening to said second conductivity type region; and forming ohmic contacts to said first and second conductivity type regions via said respective contact openings.
Claim 3
Dependent Claim
15 words
The method as recited in claim 1 wherein said first conductivity type is P type.
Claim 4
Dependent Claim
12 words
The method as recited in claim 2 wherein said semiconductor is silicon.
Claim 5
Dependent Claim
38 words
The method as recited in claim 3 wherein said P type dopant is boron and said doping to reduce contact resistance of said P region is accomplished to achieve approximately the solid solubility limit of boron in silicon.
Claim 6
Dependent Claim
17 words
The process as recited in claim 3 wherein said insulator in said contact openings is silicon dioxide.
Claim 7
Dependent Claim
22 words
The process as recited in claim 3 wherein said insulator layer on said substrate is composed of silicon dioxide and silicon nitride.
Claim 8
Dependent Claim
45 words
The process as recited in claim 6 wherein said silicon dioxide is formed by thermally oxidizing said openings at a low temperature of 800°-900° C. and taking advantage of the differential oxidation rate of said P and N type regions exposed by said contact openings.
Claim 9
Dependent Claim
197 words
A process for forming self-aligned low resistance ohmic contacts to doped regions in a semiconductor substrate, said process comprising: providing a semiconductor substrate having at least a P type region in the surface thereof and covered with an insulator layer; forming a highly doped N (hereafter N+) type region in a surface portion of said substrate by forming a small opening in said insulator layer and introducing N type dopant into said substrate surface exposed by said opening; forming a contact opening in said insulator layer corresponding to said P type region; thermally oxidizing the resulting structure at a low temperature to form an oxide layer which is substantially thicker in said opening corresponding to said N+ region than in said contact opening corresponding to said P type region by utilizing the differential oxidation rate of said P and N+type regions; removing the oxide layer in said P contact opening while leaving in tact a sufficiently thick oxide in said opening corresponding to the N+ type region; introducing P type dopant into the P type region exposed by said P contact opening; and forming ohmic contacts with said P and N+ type regions via said corresponding openings.
Claim 10
Dependent Claim
197 words
A process for forming self-aligned low resistance ohmic contacts to doped regions in a semiconductor substrate, said process comprising: providing a semiconductor substrate having at least a P type region in the surface thereof and covered with an insulator layer; forming a highly doped N (hereafter N+) type region in a surface portion of said substrate by forming a small opening in said insulator layer and introducing N type dopant into said substrate surface exposed by said opening; forming a contact opening in said insulator layer corresponding to said P type region; thermally oxidizing the resulting structure at a low temperature to form an oxide layer which is substantially thicker in said opening corresponding to said N+ region than in said contact opening corresponding to said P type region by utilizing the differential oxidation rate of said P and N+type regions; removing the oxide layer in said P contact opening while leaving in tact a sufficiently thick oxide in said opening corresponding to the N+ type region; introducing P type dopant into the P type region exposed by said P contact opening; and forming ohmic contacts with said P and N+ type regions via said corresponding openings.
Claim 11
Dependent Claim
21 words
The process as in claim 8 wherein said N+ region is formed in a surface portion of said P type region.
Claim 12
Dependent Claim
12 words
The process as in claim 9 wherein said semiconductor is monocrystalline silicon.
Claim 13
Dependent Claim
36 words
The process as in claim 10 wherein said P type and N+ regions are the base and emitter of a vertical NPN transistor, said base being formed by boron doping and said emitter by arsenic doping.
Claim 14
Dependent Claim
29 words
The process as in claim 11 wherein the thickness of the oxide in the emitter contact region is about 3-5 times thicker than that in the base contact opening.
Claim 15
Dependent Claim
27 words
The process as in claim 12 wherein the surface concentration of said base contact doping is as high as the solid solubility limit of boron in silicon.
Claim 16
Dependent Claim
18 words
The process as in claim 13 wherein said low temperature is in the range of about 800°-900° C.
Claim 17
Independent Claim
202 words
A method of forming a semiconductor device on a silicon substrate surface, comprising: forming a P type base region on a portion of said substrate surface and an insulator layer covering said substrate surface; forming a first opening in said insulator layer exposing a portion of the base region; forming an N type high dopant concentration emitter in a surface portion of said base region by introducing dopant into said exposed portion of the base region; forming a second opening in said insulator layer to expose a second portion of said base region where base contact is desired; thermally oxidizing at a low temperature to form oxide layers over said emitter and base portion exposed by said second opening, the oxide over said emitter being substantially thicker than that over said base contact due to the differential oxidation rate of said emitter and base contact regions; removing said oxide over said base contact region while maintaining a substantial thickness of said oxide over said emitter; introducing P type dopant into said base contact region to reduce contact resistance of said base; removing said substantial thickness of oxide over said emitter; and establishing ohmic contacts with said base contact region and emitter region.
Claim 18
Independent Claim
202 words
A method of forming a semiconductor device on a silicon substrate surface, comprising: forming a P type base region on a portion of said substrate surface and an insulator layer covering said substrate surface; forming a first opening in said insulator layer exposing a portion of the base region; forming an N type high dopant concentration emitter in a surface portion of said base region by introducing dopant into said exposed portion of the base region; forming a second opening in said insulator layer to expose a second portion of said base region where base contact is desired; thermally oxidizing at a low temperature to form oxide layers over said emitter and base portion exposed by said second opening, the oxide over said emitter being substantially thicker than that over said base contact due to the differential oxidation rate of said emitter and base contact regions; removing said oxide over said base contact region while maintaining a substantial thickness of said oxide over said emitter; introducing P type dopant into said base contact region to reduce contact resistance of said base; removing said substantial thickness of oxide over said emitter; and establishing ohmic contacts with said base contact region and emitter region.
Claim 19
Dependent Claim
18 words
The process as in claim 15 wherein said base is P type and said emitter is N type.
Claim 20
Dependent Claim
24 words
The process as in claim 16 wherein the dopant concentration of said emitter is in the range 0.5×10 20 atoms/cc to 3×10 20 atoms/cc.
Claim 21
Dependent Claim
21 words
The process as in claim 17 wherein the dopant concentration of said base region is in the range (2-6)×10 18 atoms/cc.
Claim 22
Dependent Claim
30 words
The process as in claim 18 wherein the dopant concentration in the base contact after introducing said dopant into said base contact is in the range of (0.5-1)×10 20 atoms/cc.
Claim 23
Dependent Claim
18 words
The process as in claim 19 wherein said insulator layer is composed of silicon dioxide and silicon nitride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-04 | 1991-07-06 | 1992-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-04 | 1995-07-06 | 1996-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-04 | 1999-07-06 | 2000-01-05 | $7700.00 | Window Closed / Lapsed |