Testability circuits for logic circuit arrays

Claim 2

An integrated circuit including: an array of identical logic function circuits which may be mask programmed to perform any one of a plurality of combinatorial and sequential logic functions, said integrated circuit configured to permit mask programmable connections between said logic function circuits in a random fashion, each of said logic function circuits including an input section including a plurality of inputs and an output node, said input section configured to produce an output value at said output node which is a selected function of input values presented to one or more of said plurality of inputs, each of said logic function circuits including an output section including an input node and an output; latching means, disposed in each of said logic function circuits, each latching means for selectively latching a logic state present at the output node of the input section of its logic function circuit or passing said logic state through to the input node of the output section of its logic function circuit in response to a control signal; selection means, coupled to each of said logic function circuits and responsive to signals from off of said integrated circuit, for providing said control signal to any one of said logic function circuits; means for selectively coupling a logic state related to the logic state at the output of each of said logic function circuits directly to an input/output pin of said integrated circuit; and whereby each of said logic function circuits may be individually and directly controlled and observed.

Claim 3

An integrated circuit including: an array of identical logic function circuits which may be mask programmed to perform any one of a plurality of combinatorial and sequential logic functions, said integrated circuit configured to permit mask programmable connections between said logic function circuits in a random fashion, each of said logic function circuits including an input section including a plurality of inputs and an output node, said input section configured to produce an output value at said output node which is a selected function of input values presented to one or more of said plurality of inputs, each of said logic function circuits including an output section including an input node and an output; latching means, disposed in each of said logic function circuits, each latching means for selectively latching a logic state present at the output node of the input section of its logic function circuit or passing said logic state through to the input node of the output section of its logic function circuit in response to a control signal; selection means, coupled to each of said logic function circuits and responsive to signals from off of said integrated circuit, for providing said control signal to any one of said logic function circuits; a test data input node in each of said logic function circuits; logic state input means, directly coupled between an input/output pin on said integrated circuit and said test data input node in each of said logic function circuits, for presenting a user-selectable logic state to each one of said logic function circuits; test data input gating means in each of said logic function circuits, each data test value input gating means for selectively passing a test data value from said test data input node in its logic function circuit to the input node of the output section of its logic function circuit in response to signals generated from off of said integrated circuit and; whereby each of said logic function circuits may be individually and directly controlled.

Claim 4

An integrated circuit including: an array of identical logic function circuits which may be mask programmed to perform any one of a plurality of combinatorial and sequential logic functions, said integrated circuit configured to permit mask programmable connections between said logic function circuits in a random fashion, each of said logic function circuits including an input section including a plurality of inputs and an output node, said input section configured to produce an output value at said output node which is a selected function of input values presented to one or more of said plurality of inputs, each of said logic function circuits including an output section including an input node and an output; latching means, disposed in each of said logic function circuits, each latching means for selectively latching a logic state present at the output node of the input section of its logic function circuit or passing said logic state through to the input node of the output section of its logic function circuit in response to a control signal; selection means, coupled to each of said logic function circuits and responsive to signals from off of said integrated circuit, for providing said control signal to any one of said logic function circuits; a test data input node in each of said logic function circuits; logic state input means, directly coupled between an input/output pin on said integrated circuit and said test data input node in each of said logic function circuits, for presenting a user-selectable logic state to each one of said logic function circuits; test data input gating means in each of said logic function circuits, each data test value input gating means for selectively passing a test data value from said test data input node in its logic function circuit to the input node of the output section of its logic function circuit in response to signals generated from off of said integrated circuit and; whereby each of said logic function circuits may be individually and directly controlled.

Claim 5

The circuitry of claim 2, further including: means for selectively coupling a logic state related to the logic state at the output of each of said logic function circuits directly to an input/output pin of said integrated circuit; whereby each of said logic function circuits may be individually and directly observed.

Claim 6

An integrated circuit including: an array of identical logic function circuits which may be mask programmed to perform any one of a plurality of combinatorial and sequential logic functions, said integrated circuit configured to permit mask programmable connections between said logic function circuits in a random fashion, each of said logic function circuits including an input section including a plurality of inputs and an output node, said input section configured to produce an output value at said output node which is a selected function of input values presented to one or more of said plurality of inputs, each of said logic function circuits including an output section including an input node and an output, said output of said output section of at least some of said function circuit modules hardwired to at least one of said plurality of inputs of said input section of another of said function circuit modules further including: latching means, disposed in each of said logic function circuits, each latching means for selectively latching a logic state present at the output node of the input section of its logic function circuit or passing said logic state through to the input node of the output section of its logic function circuit in response to a control signal; selection means, coupled to each of said logic function circuits and responsive to signals from off of said integrated circuit, for providing said control signal to any one of said logic function circuits; and whereby each of said logic function circuits may be individually and directly controlled.

Claim 7

An integrated circuit including: an array of identical logic function circuits which may be mask programmed to perform any one of a plurality of combinatorial and sequential logic functions, said integrated circuit configured to permit mask programmable connections between said logic function circuits in a random fashion, each of said logic function circuits including an input section including a plurality of inputs and an output node, said input section configured to produce an output value at said output node which is a selected function of input values presented to one or more of said plurality of inputs, each of said logic function circuits including an output section including an input node and an output, said output of said output section of at least some of said function circuit modules hardwired to at least one of said plurality of inputs of said input section of another of said function circuit modules further including: latching means, disposed in each of said logic function circuits, each latching means for selectively latching a logic state present at the output node of the input section of its logic function circuit or passing said logic state through to the input node of the output section of its logic function circuit in response to a control signal; selection means, coupled to each of said logic function circuits and responsive to signals from off of said integrated circuit, for providing said control signal to any one of said logic function circuits; and whereby each of said logic function circuits may be individually and directly controlled.