US5012185A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit having I/O terminals allowing independent connection test
Assignee: NEC Corp
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Filing: 1989-10-16
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Granted: 1991-04-30
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Expires: 2009-10-16
Abstract
Abstract A semiconductor integrated circuit comprises a plurality of input/output terminals, a test mode input circuit having a mode setting input and for generating a mode control signal, a plurality of test buffer circuits provided for the input/output terminals in one-to-one relation and each having a first terminal connected to a corresponding input/output terminal and a second terminal connected to receive a signal to be supplied to the corresponding input/output terminal or to output a signal inputted through the corresponding input/output terminal. Each test buffer circuit also includes a mode control input connected to receive the mode control signal from the test mode input circuit. When the mode control signal is in a first condition, each test buffer circuit operates to supply a predetermined logical to the corresponding input/output terminal so that the predetermined logical signal is outputted from all the input/output terminals. When the mode control signal is in a second condition different from the first condition, each test buffer circuit operates to output a signal supplied to the first or second terminal to the second or first terminal.
Inventors
- 👤 Kazuyoshi Ohfuji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701; G01R31/31712; G01R31/31713; G11; G11C; G11C7/00; G11C7/10; G11C7/1048
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
310 words
A semiconductor integrated circuit comprising a plurality of input/output terminals, at least one mode setting input terminal, a test mode input circuit having at least one mode setting input connected to said at least one mode setting input terminal to receive at least one mode setting signal and for generating at least one mode control signal, a plurality of test buffer circuits provided for said input/output terminals in one-to-one relation and each having a first terminal connected to a corresponding input/output terminal, and a second terminal connected to receive a signal to be supplied from an internal circuit of the integrated circuit to the corresponding input/output terminal or to output to an internal circuit of the integrated circuit a signal inputted through the corresponding input/output terminal from an external circuit of the integrated circuit, each test buffer circuit also including at least one mode control input connected to receive said at least one mode control signal from the test mode input circuit and operating to supply a predetermined output signal to the corresponding input/output terminal when the mode control signal is in a first condition, so that the predetermined output signal is outputted from all the input/output terminals, each test buffer circuit also operating when the mode control signal is in a second condition different from the first condition to output to the second terminal a signal supplied to the first terminal in the case of said second terminal being connected to output to the internal circuit of the integrated circuit the signal inputted through the corresponding input/output terminal from an external circuit of the integrated circuit, or to output to the first terminal a signal supplied to the second terminal in the case of said second terminal being connected to receive the signal to be supplied to the corresponding input/output terminal from an external circuit of the integrated circuit.
Claim 2
Dependent Claim
310 words
A semiconductor integrated circuit comprising a plurality of input/output terminals, at least one mode setting input terminal, a test mode input circuit having at least one mode setting input connected to said at least one mode setting input terminal to receive at least one mode setting signal and for generating at least one mode control signal, a plurality of test buffer circuits provided for said input/output terminals in one-to-one relation and each having a first terminal connected to a corresponding input/output terminal, and a second terminal connected to receive a signal to be supplied from an internal circuit of the integrated circuit to the corresponding input/output terminal or to output to an internal circuit of the integrated circuit a signal inputted through the corresponding input/output terminal from an external circuit of the integrated circuit, each test buffer circuit also including at least one mode control input connected to receive said at least one mode control signal from the test mode input circuit and operating to supply a predetermined output signal to the corresponding input/output terminal when the mode control signal is in a first condition, so that the predetermined output signal is outputted from all the input/output terminals, each test buffer circuit also operating when the mode control signal is in a second condition different from the first condition to output to the second terminal a signal supplied to the first terminal in the case of said second terminal being connected to output to the internal circuit of the integrated circuit the signal inputted through the corresponding input/output terminal from an external circuit of the integrated circuit, or to output to the first terminal a signal supplied to the second terminal in the case of said second terminal being connected to receive the signal to be supplied to the corresponding input/output terminal from an external circuit of the integrated circuit.
Claim 3
Dependent Claim
189 words
A semiconductor integrated circuit claimed in claim 1 wherein the test mode input circuit has first and second mode setting inputs for receiving first and second mode setting signals, respectively, and operates to generate first and second mode control signals on first and second mode control lines formed in the integrated circuit, and wherein each test buffer circuit has first and second mode control inputs connected to the first and second mode control lines, so that when both of the first and second mode control signals are at a first logical value, each test buffer circuit operates to output a signal supplied to the first or second terminal to the second or first terminal, and when only one of the first and second mode control signals are at a second logical value different from the first logical value, each test buffer circuit operates to supply the first or second logical value to the corresponding input/output terminal so that the first or second logical value is outputted from all the input/output terminals, regardless of a logical value of a signal supplied or to be supplied through the corresponding input/output terminal.
Claim 4
Dependent Claim
137 words
A semiconductor integrated circuit claimed in claim 2 wherein when the first mode control signal is at the second logical value and the second mode control signal is at the first logical value, each test buffer circuit operates to supply the second logical value to the corresponding input/output terminal so that the second logical value is outputted from all the input/output terminals, regardless of a logical value of a signal supplied or to be supplied through corresponding input/output terminal, and when the second mode control signal is at the second logical value and the first mode control signal is at the first logical value, each test buffer circuit operates to supply the first logical value to the corresponding input/output terminals, regardless of a logical value of a signal supplied or to be supplied through corresponding input/output terminal.
Claim 5
Dependent Claim
116 words
A semiconductor integrated circuit claimed in claim 2 wherein one of the test buffer circuits includes a CMOS inverting buffer composed of a PMOS transistor and a NMOS transistor having commonly connected gates connected to an input terminal and also having commonly connected drains connected to an internal circuit formed in the integrated circuit, and a CMOS circuit composed of a PMOS transistor and a NMOS transistor having commonly connected drains connected to the input terminal, a gate of the PMOS transistor of the CMOS circuit being connected through an inverter to the first mode control line, and a gate of the NMOS transistor of the CMOS circuit being connected to the second mode control line.
Claim 6
Dependent Claim
162 words
A semiconductor integrated circuit claimed in claim 2 wherein one of the test buffer circuits includes a pre-buffer having a first input connected to receive an internal signal from an internal circuit of the integrated circuit, and second and third inputs connected to the first and second control lines, respectively, and an output buffer having an input connected to an output of the pre-buffer and an output connected to an output terminal, the pre-buffer operating in such a manner that when both of the first and second mode control signals are at the first logical value, the output buffer outputs a signal supplied to the first input of the pre-buffer to the output terminal, and when only one of the first and second mode control signals is at the second logical value, the output buffer outputs the first or second logical value to the output terminal, regardless of a logical value of a signal supplied to the first input of the pre-buffer.
Claim 7
Dependent Claim
205 words
A semiconductor integrated circuit claimed in claim 2 wherein one of the test buffer circuits includes a pre-buffer having a first input connected to receive an internal signal from an internal circuit of the integrated circuit, second and third inputs connected to the first and second control lines, respectively, and a fourth input connected to receive an enable signal, and an CMOS output buffer having first and second inputs connected to first and second outputs of the pre-buffer, respectively and an output connected to an output terminal, the pre-buffer operating in such a manner that when both of the first and second mode control signals are at the first logical value, the output buffer outputs a signal supplied to the first input of the pre-buffer to the output terminal if the enable signal is active and to bring the output terminal into a high impedance if the enable signal is inactive, and when only one of the first and second mode control signals is at the second logical value, the output buffer outputs the first or second logical value to the output terminal, regardless of a logical value of a signal supplied to the first input of the pre-buffer and regardless of the enable signal.
Claim 8
Dependent Claim
60 words
A semiconductor integrated circuit claimed in claim 3 wherein when both of the first and second mode control signals are at the second logical value, each test buffer circuit operates to cause to bring the corresponding input/output terminal into a high impedance condition, regardless of a logical value of a signal supplied or to be supplied through corresponding input/output terminal.
Claim 9
Dependent Claim
207 words
A semiconductor integrated circuit claimed in claim 7 wherein one of the test buffer circuits includes a pre-buffer having a first input connected to receive an internal signal from an internal circuit of the integrated circuit, and second and third inputs connected to the first and second control lines, respectively, and an CMOS output buffer having first and second inputs connected to first and second outputs of the pre-buffer, respectively and an output connected to an output terminal, the pre-buffer operating in such a manner that when both of the first and second mode control signals are at the first logical value, the CMOS output buffer outputs a signal supplied to the first input of the pre-buffer to the output terminal, and when only one of the first and second mode control signals is at the second logical value, the CMOS output buffer outputs the first or second logical value to the output terminal, regardless of a logical value of a signal supplied to the first input of the pre-buffer, the pre-buffer also operating in such a manner that when both of the first and second mode control signals are at the second logical value, the CMOS output buffer brings the output terminal into a high impedance.
Claim 10
Dependent Claim
250 words
A semiconductor integrated circuit claimed in claim 7 wherein one of the test buffer circuits includes a pre-buffer having a first input connected to receive an internal signal from an internal circuit of the integrated circuit, second and third inputs connected to the first and second control lines, respectively, and a fourth input connected to receive an enable signal, and an CMOS output buffer having first and second inputs connected to first and second outputs of the pre-buffer, respectively and an output connected to an output terminal, the pre-buffer operating in such a manner that when both of the first and second mode control signals are at the first logical value, the output buffer outputs a signal supplied to the first input of the pre-buffer to the output terminal if the enable signal is active, and when only one of the first and second mode control signals is at the second logical value, the output buffer outputs the first or second logical value to the output terminal, regardless of a logical value of a signal supplied to the first input of the pre-buffer and regardless of the enable signal, the pre-buffer also operating in such a manner that the CMOS output buffer brings the output terminal into a high impedance when both of the first and second mode control signals are at the second logical value, or when both of the first and second mode control signals are at the first logical value but if the enable signal is inactive.
Claim 11
Dependent Claim
85 words
A semiconductor integrated circuit claimed in claim 2 wherein in each pair of adjacent test buffer circuits, if one of the adjacent test buffer circuits has the first mode control input connected to the first mode control line and the second mode control input connected to the second mode control line, the other of the adjacent test buffer circuits has the first mode control input connected to the second mode control line and the second mode control input connected to the first mode control line.
References Cited (Backward Citations)
US4339710A
Cited
US4743841A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |