Ball grid array integrated circuit package with thermal conductor

Claim 2

A packaged integrated circuit device, comprising: an interconnection substrate having one layer of conductive trace material and one layer of insulating material formed in or on said interconnection substrate, wherein said interconnection substrate has a first surface and a second surface opposite said first surface, said second surface of said interconnection substrate having a plurality of electrical contacts arranged in rows that are electrically connected to said one layer of conductive trace material for making electrical connections from said conductive trace material to contact points external to said packaged integrated circuit device; a metallic thermal conductor, said thermal conductor having a first surface attached to said first surface of said interconnection substrate, said thermal conductor having a second surface opposite said first surface, which is exposed to the exterior of said packaged integrated circuit device, wherein a thickness of said thermal conductor between said first surface and said second surface of said thermal conductor is less than 1.0 millimeter, and said thermal conductor is linearly co-extensive with said interconnection substrate first surface; a well region formed in said interconnection substrate, said well region having a bottom which is an exposed portion of said first surface of said thermal conductor; an integrated circuit chip, said integrated circuit chip having a first surface and a second surface opposite said first surface, said integrated circuit chip being attached in said well region such that said second surface of said integrated circuit chip and said portion of said first surface of said thermal conductor exposed at said bottom of said well region are adhesively attached; and a plurality of conductive bond wires, said bond wires making electrical connections between said integrated circuit chip and bonding locations on said one layer of conductive trace material, wherein said packaged integrated circuit device has a thickness of less than 2.3 millimeters.

Claim 3

The packaged integrated circuit device of claim 1, wherein: said first surface of said thermal conductor is treated to form an adhesion layer.

Claim 4

The packaged integrated circuit device of claim 2, wherein: said adhesion layer is a black oxide layer.

Claim 5

The packaged integrated circuit device of claim 1, wherein: said thermal conductor is copper.

Claim 6

The packaged integrated circuit device of claim 1, wherein: said thermal conductor is aluminum.

Claim 7

The packaged integrated circuit device of claim 1, wherein: said plurality of electrical contacts on said second surface of said interconnection substrate are balls.

Claim 8

The packaged integrated circuit device of claim 6, wherein: said plurality of balls on said second surface of said interconnection substrate are solder balls.

Claim 9

The packaged integrated circuit device of claim 1, wherein: said interconnection substrate further comprises: two or more layers of insulating material; and two or more layers of conductive trace material, wherein each of said two or more layers of insulating material alternate with each of said two or more layers of conductive trace material; and said two or more layers of conductive trace material are electrically connected to said plurality of electrical contacts for making electrical connections from said conductive trace material to contact points external to said packaged integrated circuit device.

Claim 10

The packaged integrated circuit device of claim 8, wherein: said interconnection substrate further comprises: a metal layer attached to said thermal conductor, wherein said one layer of insulating material is attached to said metal layer; and said one layer of conductive trace material is attached to said insulating layer.

Claim 11

The packaged integrated circuit device of claim 1, further comprising: a lid, said lid being positioned and attached to said second surface of said interconnection substrate such that said lid covers said well region of said interconnection substrate, said integrated circuit chip, and said plurality of conductive bond wires.

Claim 12

The packaged integrated circuit device of claim 1, wherein: said well region of said interconnection substrate is filled to a predetermined level with an electrically insulating encapsulant material such that said bond wires and said integrated circuit chip are covered by said electrically insulating encapsulant material.

Claim 13

The packaged integrated circuit device of claim 11, further comprising: a dam positioned around the perimeter of said well region of said interconnection substrate to contain said insulating encapsulant material.

Claim 14

The packaged integrated circuit device of claim 12, wherein: said dam is a plastic resin.

Claim 15

The packaged integrated circuit device of claim 12, wherein: said dam is a tape.

Claim 16

The packaged integrated circuit device of claim 12, wherein: said interconnection substrate further comprises: a metal layer attached to said thermal conductor, wherein said one layer of insulating material is attached to said metal layer; and said one layer of conductive trace material is attached to said insulating layer.

Claim 17

The packaged integrated circuit device of claim 15, wherein: said metal layer of said interconnection substrate is copper.

Claim 18

The packaged integrated circuit device of claim 12, wherein: said interconnection substrate further comprises: two or more layers of insulating material; and two or more layers of conductive trace material, wherein each of said two or more layers of insulating material alternate with each of said two or more layers of conductive trace material; and said two or more layers of conductive trace material are electrically connected to said plurality of electrical contacts for making electrical connections from said conductive trace material to contact points external to said packaged integrated circuit device.

Claim 19

A packaged integrated circuit device, comprising: a metallic thermal conductor, said thermal conductor having a first surface and a second surface opposite said first surface, which is exposed to the exterior of said packaged integrated circuit device, a thickness of said thermal conductor between said first surface and said second surface being less than 1.0 millimeter; a first insulating layer, said first insulating layer being applied directly to said first surface of said thermal conductor; a first layer of conductive trace material, said first layer of conductive trace material being applied over said first insulating layer; an interconnection substrate having one layer of conductive trace material and one layer of insulating material formed in or on said interconnection substrate, wherein said interconnection substrate has a first surface and a second surface opposite said first surface, said first surface of said interconnection substrate being attached to said first layer of conductive trace material, said second surface of said interconnection substrate having a plurality of electrical contacts arranged in rows for making electrical connections from said first layer of conductive trace material and said one layer of conductive trace material to contact points external to said packaged integrated circuit device, wherein said thermal conductor is linearly co-extensive with said interconnection substrate; a well region formed in said interconnection substrate, said well region having a bottom which is an exposed portion of said first conductive trace layer; an integrated circuit chip, said integrated circuit chip having a first surface and a second surface opposite said first surface, said integrated circuit chip being attached in said well region in a flip-chip configuration such that said first surface of said integrated circuit chip is attached to said exposed portion of said first conductive trace layer at said bottom of said well region, wherein said packaged integrated circuit device has a thickness of less than 2.3 millimeters.

Claim 20

A packaged integrated circuit device, comprising: a metallic thermal conductor, said thermal conductor having a first surface and a second surface opposite said first surface, which is exposed to the exterior of said packaged integrated circuit device, a thickness of said thermal conductor between said first surface and said second surface being less than 1.0 millimeter; a first insulating layer, said first insulating layer being applied directly to said first surface of said thermal conductor; a first layer of conductive trace material, said first layer of conductive trace material being applied over said first insulating layer; an interconnection substrate having one layer of conductive trace material and one layer of insulating material formed in or on said interconnection substrate, wherein said interconnection substrate has a first surface and a second surface opposite said first surface, said first surface of said interconnection substrate being attached to said first layer of conductive trace material, said second surface of said interconnection substrate having a plurality of electrical contacts arranged in rows for making electrical connections from said first layer of conductive trace material and said one layer of conductive trace material to contact points external to said packaged integrated circuit device, wherein said thermal conductor is linearly co-extensive with said interconnection substrate; a well region formed in said interconnection substrate, said well region having a bottom which is an exposed portion of said first conductive trace layer; an integrated circuit chip, said integrated circuit chip having a first surface and a second surface opposite said first surface, said integrated circuit chip being attached in said well region in a flip-chip configuration such that said first surface of said integrated circuit chip is attached to said exposed portion of said first conductive trace layer at said bottom of said well region, wherein said packaged integrated circuit device has a thickness of less than 2.3 millimeters.

Claim 21

The packaged integrated circuit device of claim 18, wherein: said first surface of said thermal conductor is treated to form an adhesion layer.

Claim 22

The packaged integrated circuit device of claim 19, wherein: said adhesion layer is a black oxide layer.

Claim 23

The packaged integrated circuit device of claim 18, wherein: said thermal conductor is copper.

Claim 24

The packaged integrated circuit device of claim 18, wherein: said thermal conductor is aluminum.

Claim 25

The packaged integrated circuit device of claim 18, wherein: said plurality of electrical contacts on said second surface of said interconnection substrate are balls.

Claim 26

The packaged integrated circuit device of claim 23, wherein: said plurality of balls on said second surface of said interconnection substrate are solder balls.

Claim 27

The packaged integrated circuit device of claim 18, wherein: said interconnection substrate further comprises: two or more layers of insulating material; and two or more layers of conductive trace material, wherein each of said two or more layers of insulating material alternate with each of said two or more layers of conductive trace material; and said two or more layers of conductive trace material are electrically connected to said plurality of electrical contacts for making electrical connections from said conductive trace material to contact points external to said packaged integrated circuit device.

Claim 28

The packaged integrated circuit device of claim 18, further comprising: a lid, said lid being positioned and attached to said second surface of said interconnection substrate such that said lid covers said well region of said interconnection substrate and said integrated circuit chip.

Claim 29

The packaged integrated circuit device of claim 18, wherein: said well region of said interconnection substrate is filled to a predetermined level with an electrically insulating encapsulant material.

Claim 30

A packaged integrated circuit device, comprising: a metallic thermal conductor, said thermal conductor having a first surface and a second surface opposite said first surface, which is exposed to the exterior of said packaged integrated circuit device, a thickness of said thermal conductor between said first surface and said second surface being less than 1.0 millimeter; a first insulating layer, said first insulating layer being applied directly to said first surface of said thermal conductor; a first layer of conductive trace material, said first layer of conductive trace material being applied over said first insulating layer; an integrated circuit chip, said integrated circuit chip having a first surface and a second surface opposite said first surface, said integrated circuit chip being attached to a portion of said first conductive trace layer in a flip-chip configuration; and a dam, said dam being applied to said first layer of conductive trace material such that said dam is positioned around the perimeter of said integrated circuit chip, thereby creating a well region around said integrated circuit chip, wherein said packaged integrated circuit device has a thickness of less than 2.3 millimeters.

Claim 31

A packaged integrated circuit device, comprising: a metallic thermal conductor, said thermal conductor having a first surface and a second surface opposite said first surface, which is exposed to the exterior of said packaged integrated circuit device, a thickness of said thermal conductor between said first surface and said second surface being less than 1.0 millimeter; a first insulating layer, said first insulating layer being applied directly to said first surface of said thermal conductor; a first layer of conductive trace material, said first layer of conductive trace material being applied over said first insulating layer; an integrated circuit chip, said integrated circuit chip having a first surface and a second surface opposite said first surface, said integrated circuit chip being attached to a portion of said first conductive trace layer in a flip-chip configuration; and a dam, said dam being applied to said first layer of conductive trace material such that said dam is positioned around the perimeter of said integrated circuit chip, thereby creating a well region around said integrated circuit chip, wherein said packaged integrated circuit device has a thickness of less than 2.3 millimeters.

Claim 32

The packaged integrated circuit device of claim 28, further comprising: a plurality of electrical contacts arranged in rows for making electrical connections from said first layer of conductive trace material to contact points external to said packaged integrated circuit device.

Claim 33

The packaged integrated circuit device of claim 29, wherein: said first surface of said thermal conductor is treated to form an adhesion layer.

Claim 34

The packaged integrated circuit device of claim 30, wherein: said adhesion layer is a black oxide layer.

Claim 35

The packaged integrated circuit device of claim 29, wherein: said thermal conductor is copper.

Claim 36

The packaged integrated circuit device of claim 29, wherein: said thermal conductor is aluminum.

Claim 37

The packaged integrated circuit device of claim 29, wherein: said plurality of electrical contacts on said second surface of said interconnection substrate are balls.

Claim 38

The packaged integrated circuit device of claim 34, wherein: said plurality of balls on said second surface of said interconnection substrate are solder balls.

Claim 39

The packaged integrated circuit device of claim 29, wherein: said dam is a plastic resin.

Claim 40

The packaged integrated circuit device of claim 29, wherein: said dam is a tape.

Claim 41

The packaged integrated circuit device of claim 29, wherein: said well region around said integrated circuit chip, created by said dam, is filled to a predetermined level with an electrically insulating encapsulant material.

Claim 42

The packaged integrated circuit device of claim 28, further comprising: a second insulating layer, said second insulating layer being applied over said first conductive trace layer; and a second conductive trace layer, said second conductive trace layer being applied over said second insulating layer, wherein said dam is applied to said second layer of conductive trace material such that said dam is positioned around the perimeter of said integrated circuit chip, thereby creating a well region around said integrated circuit chip.

Claim 43

The packaged integrated circuit device of claim 39, further comprising: a plurality of electrical contacts arranged in rows for making electrical connections from said second layer of conductive trace material to contact points external to said packaged integrated circuit device.