Leadless pad array chip carrier

Claim 2

A leadless pad array chip carrier package, comprising: a leadless circuit carrying insulating substrate having opposing planar first and second sides; a semiconductor device electrically and mechanically mounted on the first side of the circuit carrying substrate; the substrate second side having a substantially coplanar array of surface mount solder pads arranged in checkerboard fashion to substantially cover the substrate second side, a portion of the array disposed below the semiconductor device; the semiconductor device electrically connected to the surface mount solder pads by means of vias through the leadless circuit carrying substrate, each of said vias positioned away from said surface mount solder pads; and a protective cover consisting of a resin transfer molded about the semiconductor device and covering a portion of the first side of the leadless circuit carrying substrate, to form a leadless pad array chip carrier.

Claim 3

The leadless pad array chip carrier package of claim 1, wherein the protective cover is smaller than the leadless circuit carrying insulating substrate, thereby exposing a portion of the first side of the leadless circuit carrying insulating substrate about a perimeter of the protective cover.

Claim 4

The leadless pad array chip carrier package of claim 1, wherein the leadless circuit carrying insulating substrate is a glass reinforced printed circuit board.

Claim 5

The leadless pad array chip carrier package of claim 1, wherein the leadless circuit carrying insulating substrate is a flexible film.

Claim 6

The leadless pad array chip carrier package of claim 4, wherein the flexible film is selected from the group consisting of polyimide, polyester, or polyetherimide.

Claim 7

The leadless pad array chip carrier package of claim 1, wherein the semiconductor device is wirebonded to the leadless circuit carrying insulating substrate.

Claim 8

The leadless pad array chip carrier package of claim 1, wherein the semiconductor device is tape automated bonded (TAB) to the leadless circuit carrying insulating substrate.

Claim 9

The leadless pad array chip carrier package of claim 1, wherein the semiconductor device is directly attached to the leadless circuit carrying insulating substrate.

Claim 10

The leadless pad array chip carrier package of claim 1, wherein the protective cover is a thermosetting resin or a thermoplastic resin.

Claim 11

A leadless pad array chip carrier package, comprising: a leadless circuit carrying insulating substrate having opposing planar first and second sides; a semiconductor device electrically and mechanically mounted on the first side of the circuit carrying substrate; the substrate second side having a substantially coplanar array of surface mount solder pads arranged in checkerboard fashion to substantially cover the substrate second side, a portion of the array disposed below the semiconductor device; solder bumps on the solder pads; the semiconductor device electrically connected to the surface mount solder pads by means of vias through the leadless circuit carrying substrate, each of said vias positioned away from said surface mount solder pads; and a protective cover consisting of a resin transfer molded about the semiconductor device and covering a portion of the first side of the leadless circuit carrying substrate, to form a leadless pad array chip carrier.

Claim 12

A leadless pad array chip carrier package, comprising: a leadless circuit carrying insulating substrate having opposing planar first and second sides; a semiconductor device electrically and mechanically mounted on the first side of the circuit carrying substrate; the substrate second side having a substantially coplanar array of surface mount solder pads arranged in checkerboard fashion to substantially cover the substrate second side, a portion of the array disposed below the semiconductor device; solder bumps on the solder pads; the semiconductor device electrically connected to the surface mount solder pads by means of vias through the leadless circuit carrying substrate, each of said vias positioned away from said surface mount solder pads; and a protective cover consisting of a resin transfer molded about the semiconductor device and covering a portion of the first side of the leadless circuit carrying substrate, to form a leadless pad array chip carrier.

Claim 13

A leadless pad array chip carrier package, comprising: a printed circuit board having planar opposing first and second sides, said first side having a metallization pattern; at least one semiconductor device mechanically attached to said metallization pattern; wire bonds electrically connecting said semiconductor device to said metallization pattern; a matrix of solder pads on and substantially coplanar to said printed circuit board second side, arranged in checkerboard fashion to substantially cover the substrate second side, a portion of said matrix under said semiconductor device; conductive vias in the printed circuit board electrically connecting the matrix of solder pads to the metallization pattern, each of said conductive vias positioned away from said solder pads; solder bumps on said solder pads; and a cover consisting of a thermosetting plastic resin transfer molded about said at least one semiconductor device and said wire bonds, and substantially covering said printed circuit board first side, said cover being smaller than said printed circuit board, thereby exposing a portion of said printed circuit board first side about a perimeter of said cover to form a leadless pad array chip carrier.

Claim 14

A leadless pad array chip carrier package, comprising: a printed circuit board having planar opposing first and second sides, said first side having a metallization pattern; at least one semiconductor device mechanically attached to said metallization pattern; wire bonds electrically connecting said semiconductor device to said metallization pattern; a matrix of solder pads on and substantially coplanar to said printed circuit board second side, arranged in checkerboard fashion to substantially cover the substrate second side, a portion of said matrix under said semiconductor device; conductive vias in the printed circuit board electrically connecting the matrix of solder pads to the metallization pattern, each of said conductive vias positioned away from said solder pads; solder bumps on said solder pads; and a cover consisting of a thermosetting plastic resin transfer molded about said at least one semiconductor device and said wire bonds, and substantially covering said printed circuit board first side, said cover being smaller than said printed circuit board, thereby exposing a portion of said printed circuit board first side about a perimeter of said cover to form a leadless pad array chip carrier.