Method of making a chip carrier slotted array

Claim 1

A method of making a chip carrier array comprising the steps of: providing a substrate; and forming elongated slots in the substrate which extend beyond the corners of individual chip carriers to define edges thereof and which form one severable interconnecting bridge at each edge of each chip carrier, each edge of each chip carrier including first and second edge portions separated by a respective interconnecting bridge, which bridges maintain the individual chip carriers in the chip carrier array.

Claim 2

A method of making a chip carrier array comprising the steps of: providing a substrate; and forming elongated slots in the substrate which extend beyond the corners of individual chip carriers to define edges thereof and which form one severable interconnecting bridge at each edge of each chip carrier, each edge of each chip carrier including first and second edge portions separated by a respective interconnecting bridge, which bridges maintain the individual chip carriers in the chip carrier array.

Claim 8

A method of making a chip carrier array comprising the steps of: providing a substrate having first and second surfaces; and forming elongated slots in said substrate which define outer edges of individual rectangular chip carriers and which form one severable interconnecting bridge for each edge of each chip carrier, each edge of each chip carrier including first and second edge portions separated by a respective interconnecting bridge, which bridges maintain the individual chip carriers within the array; applying a plurality of electrically isolated metallized edge interconnects to each of said first and second edge portions of each of said chip carriers which extend from the first surface thereof and wrap around the edges thereof to the second surface thereof.

Claim 9

A method of making a chip carrier array comprising the steps of: providing a substrate having first and second surfaces; and forming elongated slots in said substrate which define outer edges of individual rectangular chip carriers and which form one severable interconnecting bridge for each edge of each chip carrier, each edge of each chip carrier including first and second edge portions separated by a respective interconnecting bridge, which bridges maintain the individual chip carriers within the array; applying a plurality of electrically isolated metallized edge interconnects to each of said first and second edge portions of each of said chip carriers which extend from the first surface thereof and wrap around the edges thereof to the second surface thereof.

Claim 17

A method of making a chip carrier array comprising the steps of: providing a substrate; and forming a plurality of individual chip carriers in said substrate having outer edges and carriers defined by elongated slots which extend from single severable interconnecting bridges respectively located along each edge of each carrier and separating each chip carrier edge into first and second edge portions, which bridges maintain the individual chip carriers within the array; and forming metallized edge interconnects on each of said plurality of chip carriers.

Claim 18

A method of making a chip carrier array comprising the steps of: providing a substrate; and forming a plurality of individual chip carriers in said substrate having outer edges and carriers defined by elongated slots which extend from single severable interconnecting bridges respectively located along each edge of each carrier and separating each chip carrier edge into first and second edge portions, which bridges maintain the individual chip carriers within the array; and forming metallized edge interconnects on each of said plurality of chip carriers.

Claim 19

A method of making a chip carrier array comprising the steps of: providing a substrate; forming a plurality of individual chip carriers in said substrate having top and bottom surfaces and having outer edges and corners defined by elongated slots which extend from single severable interconnecting bridges respectively located along each edge of each carrier and separating each chip carrier edge into first and second edge portions, which bridges maintain the individual chip carriers within said array; forming a first portion of overlapping electrically isolated metallized edge interconnects which comprises a first metallization pattern which extends from the top surfaces of said chip carriers and wraps around the edges formed by said elongated slots and extends a predetermined distance across said edges; and forming a second portion of said electrically isolated metallized edge interconnects which comprises a second metallization pattern which extends from the bottom surfaces of said chip carriers and wraps around the edges formed by said elongated slots and overlaps said first metallization pattern to form a continuous electrically isolated edge metallization pattern which wraps around the edges of said chip carriers.

Claim 20

A method of making a chip carrier array comprising the steps of: providing a substrate; forming a plurality of individual chip carriers in said substrate having top and bottom surfaces and having outer edges and corners defined by elongated slots which extend from single severable interconnecting bridges respectively located along each edge of each carrier and separating each chip carrier edge into first and second edge portions, which bridges maintain the individual chip carriers within said array; forming a first portion of overlapping electrically isolated metallized edge interconnects which comprises a first metallization pattern which extends from the top surfaces of said chip carriers and wraps around the edges formed by said elongated slots and extends a predetermined distance across said edges; and forming a second portion of said electrically isolated metallized edge interconnects which comprises a second metallization pattern which extends from the bottom surfaces of said chip carriers and wraps around the edges formed by said elongated slots and overlaps said first metallization pattern to form a continuous electrically isolated edge metallization pattern which wraps around the edges of said chip carriers.

Claim 24

A method of mounting electronic chips on interconnected individual chip carriers to form interconnected mounted chip carrier assemblies, and electrically testing the interconnected mounted chip carrier assemblies, said method comprising the steps of: providing a chip carrier array comprising a plurality of chip carriers having top and bottom surfaces and having outer edges defined by slots extending from single severable interconnecting bridges respectively located along each edge of each carrier and separating each chip carrier edge into first and second edge portions, which bridges maintain the chip carriers within the array; providing a plurality of electrically isolated metallized edge interconnects which wrap around the edges and portions of the top and bottom surfaces adjacent the edges; disposing a plurality of electronic chips on said plurality of individual chip carriers; and electrically coupling said electronic chips to selected ones of said metallized edge interconnects to form mounted carrier assemblies; electrically testing said mounted carrier assemblies for electrical performance.

Claim 25

A method of mounting electronic chips on interconnected individual chip carriers to form interconnected mounted chip carrier assemblies, and electrically testing the interconnected mounted chip carrier assemblies, said method comprising the steps of: providing a chip carrier array comprising a plurality of chip carriers having top and bottom surfaces and having outer edges defined by slots extending from single severable interconnecting bridges respectively located along each edge of each carrier and separating each chip carrier edge into first and second edge portions, which bridges maintain the chip carriers within the array; providing a plurality of electrically isolated metallized edge interconnects which wrap around the edges and portions of the top and bottom surfaces adjacent the edges; disposing a plurality of electronic chips on said plurality of individual chip carriers; and electrically coupling said electronic chips to selected ones of said metallized edge interconnects to form mounted carrier assemblies; electrically testing said mounted carrier assemblies for electrical performance.

Claim 26

A method of mounting electronic chips on interconnected individual chip carriers to form interconnected mounted chip carrier assemblies and electrically testing the interconnected mounted chip carrier assemblies, said method comprising the steps of: providing a chip carrier array comprising a plurality of chip carriers having top and bottom surfaces and having outer edges defined by slots extending from single severable interconnecting bridges respectively located along each edge of each carrier and separating each chip carrier edge into first and second edge portions, which bridges which maintain the chip carriers within the array; providing a plurality of electrically isolated metallized edge interconnects which wrap around the edges and portions of the top and bottom surfaces adjacent the edges; disposing a plurality of electronic chips on said plurality of individual chip carriers; electrically coupling said electronic chips to selected ones of said metallized edge interconnects to form mounted carrier assemblies; electrically testing said mounted carrier assemblies for electrical performance; and severing said bridges to physically separate said mounted carrier assemblies from one another.

Claim 27

A method of mounting electronic chips on interconnected individual chip carriers to form interconnected mounted chip carrier assemblies and electrically testing the interconnected mounted chip carrier assemblies, said method comprising the steps of: providing a chip carrier array comprising a plurality of chip carriers having top and bottom surfaces and having outer edges defined by slots extending from single severable interconnecting bridges respectively located along each edge of each carrier and separating each chip carrier edge into first and second edge portions, which bridges which maintain the chip carriers within the array; providing a plurality of electrically isolated metallized edge interconnects which wrap around the edges and portions of the top and bottom surfaces adjacent the edges; disposing a plurality of electronic chips on said plurality of individual chip carriers; electrically coupling said electronic chips to selected ones of said metallized edge interconnects to form mounted carrier assemblies; electrically testing said mounted carrier assemblies for electrical performance; and severing said bridges to physically separate said mounted carrier assemblies from one another.