US5583068A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for forming a capacitor having a metal-oxide dielectric
Assignee: NXP USA Inc
•
Filing: 1995-04-28
•
Granted: 1996-12-10
•
Expires: 2015-04-28
Abstract
Abstract A capacitor with a metal-oxide dielectric layer is formed with an upper electrode layer that is electrically connected to an underlying circuit element. The capacitor may be used in forming storage capacitors for DRAM and NVRAM cells. After forming an underlying circuit element, such as a source/drain region of a transistor, a metal-oxide capacitor is formed over the circuit element. An opening is formed through the capacitor and extends to the circuit element. An insulating spacer is formed, and a conductive member is formed that electrically connects the circuit element to the upper electrode layer of the metal-oxide capacitor. Devices including DRAM and NVRAM cells and methods of forming them are disclosed.
Inventors
- 👤 Robert E. Jones, Jr.
- 👤 Papu D. Maniar
- 👤 Andrew C. Campbell
- 👤 Reza Moazzami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:28
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
84 words
A process for forming a semiconductor device comprising the steps of: forming a circuit element; forming a capacitor overlying the circuit element, wherein: the capacitor includes a first electrode layer, a metal-oxide dielectric layer that overlies the first electrode layer, and a second electrode layer that overlies the dielectric layer; and forming a conductive member that electrically connects the circuit element and the second electrode layer to each other, wherein the conductive member extends through the first electrode and dielectric layers of the capacitor.
Claim 2
Dependent Claim
84 words
A process for forming a semiconductor device comprising the steps of: forming a circuit element; forming a capacitor overlying the circuit element, wherein: the capacitor includes a first electrode layer, a metal-oxide dielectric layer that overlies the first electrode layer, and a second electrode layer that overlies the dielectric layer; and forming a conductive member that electrically connects the circuit element and the second electrode layer to each other, wherein the conductive member extends through the first electrode and dielectric layers of the capacitor.
Claim 3
Dependent Claim
40 words
The process of claim 1, wherein the metal-oxide dielectric layer includes a material selected from a group consisting of tantalum pentoxide, zirconium titanate, barium titanate, barium strontium titanate, strontium titanate, bismuth titanate, lead zirconate titanate, and lanthanum-doped lead zirconate titanate.
Claim 4
Dependent Claim
16 words
The process of claim 1, wherein the circuit element is a source/drain region of a transistor.
Claim 5
Dependent Claim
25 words
The process of claim 1, wherein the conductive member includes a material selected from a group consisting of silicon, a refractory metal, and titanium nitride.
Claim 6
Dependent Claim
46 words
The process of claim 1, further comprising a step of forming an insulating spacer lying adjacent to the conductive member, the capacitor, and the circuit element, wherein the insulating spacer includes a material selected from a group consisting of a refractory metal oxide and magnesium oxide.
Claim 7
Dependent Claim
88 words
A process for forming a random-access memory cell comprising the steps of: forming a transistor having a source/drain region; forming a capacitor overlying the source/drain region, wherein: the capacitor includes a first electrode layer, a metal-oxide dielectric layer that overlies the first electrode layer, and a second electrode layer that overlies the dielectric layer; and forming a conductive member that electrically connects the source/drain region and the second electrode layer to each other, wherein the conductive member extends through the first electrode and dielectric layers of the capacitor.
Claim 8
Dependent Claim
88 words
A process for forming a random-access memory cell comprising the steps of: forming a transistor having a source/drain region; forming a capacitor overlying the source/drain region, wherein: the capacitor includes a first electrode layer, a metal-oxide dielectric layer that overlies the first electrode layer, and a second electrode layer that overlies the dielectric layer; and forming a conductive member that electrically connects the source/drain region and the second electrode layer to each other, wherein the conductive member extends through the first electrode and dielectric layers of the capacitor.
Claim 9
Dependent Claim
45 words
The process of claim 6, wherein: the memory cell is a dynamic-random-access memory cell; and the metal-oxide dielectric layer includes a material selected from a group consisting of tantalum pentoxide, zirconate titanate, barium strontium titanate, strontium titanate, lead zirconate titanate, and lanthanum-doped lead zirconate titanate.
Claim 10
Dependent Claim
43 words
The process of claim 6, wherein: the memory cell is a nonvolatile-random-access memory cell; and the metal-oxide dielectric layer includes a material selected from a group consisting of barium strontium titanate, barium titanate, bismuth titanate, lead zirconate titanate, and lanthanum-doped lead zirconate titanate.
Claim 11
Dependent Claim
25 words
The process of claim 6, wherein the conductive member includes a material selected from a group consisting of silicon, a refractory metal, and titanium nitride.
Claim 12
Dependent Claim
46 words
The process of claim 6 further comprising a step of forming an insulating spacer lying adjacent to the conductive member, the capacitor, and the source/drain region, wherein the insulating spacer includes a material selected from a group consisting of a refractory metal oxide and magnesium oxide.
References Cited (Backward Citations)
US4251326A
Cited
US5046043A
Cited
US5109357A
Cited
US4985718A
Cited
US4952904A
Cited
EP0396221A2
Cited
US5005102A
Cited
EP0430404A1
Cited
US5196909A
Cited
US5155573A
Cited
US5146299A
Cited
DE4107165A1
Cited
EP0493614A1
Cited
EP0516031A1
Cited
US5142437A
Cited
US5257238A
Cited
US5164808A
Cited
US5283462A
Cited
US5300799A
Cited
US5142438A
Cited
JPH05190797A
Cited
US5329486A
Cited
US5191510A
Cited
US5185689A
Cited
US5313089A
Cited
US5254217A
Cited
US5350705A
Cited
US5426561A
Cited
US5258093A
Cited
US5381302A
Cited
EP0637845A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |