EP0430404A1
Expired / Lapsed
EP
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Method of manufacturing a capacitor for a DRAM cell
Assignee: STMicroelectronics lnc USA
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Filing: 1990-08-30
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Granted: —
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Expires: 2010-08-30
Abstract
Abstract A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. First the bottom polycrystalline silicon plate layer (26)is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer(30,50). Following another isolation step, the polycrystalline silicon top plate layer(62)is then formed and connected to the bottom plate layer. The storage electrode employs a buffer polysilicon layer (30) and contacts the active region via an etched hole using sidespacer insulation(48). Sidespacers (60) are also used to isolate the outer edges of the storage electrode.
Inventors
- 👤 Tsiu Chiu Chan
- 👤 Frank Randolph Bryant
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 15:28
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10D1/684; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/32; H10P14/3202; H10P14/3214; H10P14/3216; H10P14/3224; H10P14/3226; H10P32/00; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S438/00; Y10S438/954
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
68 words
A method for fabricating an integrated circuit capacitor, comprising the steps of: forming a polycrystalline silicon lower capacitor plate; forming a first insulating layer; forming a polycrystalline silicon charge storage capacitor plate; forming a second insulating layer; exposing a portion of the polycrystalline silicon lower capacitor plate; and forming a polycrystalline silicon upper capacitor plate over the second insulating layer and in contact with the lower capacitor plate.
Claim 2
Dependent Claim
34 words
The method of Claim 1, further comprising the step of: after said first insulating layer forming step, opening a contact to a substrate, wherein the polycrystalline silicon charge storage capacitor plate contacts the substrate.
Claim 3
Dependent Claim
87 words
The method of Claim 1, wherein said first insulating layer forming step comprises the steps of: forming a horizontal insulating layer over the lower capacitor plate; forming a polycrystalline silicon buffer layer; etching a contact opening through the lower capacitor plate layer, the horizontal insulating layer, and the polycrystalline silicon buffer layer to expose a portion of an underlying substrate; forming a third insulating layer over the surface of the integrated circuit; and anisotropically etching the third insulating layer to form insulating sidewalls within the contact opening.
Claim 4
Dependent Claim
27 words
The method of Claim 3, wherein said third insulating layer forming step comprises the step of: growing a thermal oxide over the surface of the integrated circuit.
Claim 5
Dependent Claim
27 words
The method of Claim 3, wherein said third insulating layer forming step comprises the step of: depositing a CVD oxide over the surface of the integrated circuit.
Claim 6
Dependent Claim
43 words
The method of Claim 1, wherein said first insulating layer forming step comprises the steps of: forming a first oxide layer over the integrated circuit; forming a nitride layer over the oxide layer; and forming a second oxide layer over the nitride layer.
Claim 7
Dependent Claim
43 words
The method of Claim 1, wherein said second insulating layer forming step comprises the steps of: forming a first oxide layer over the integrated circuit; forming a nitride layer over the oxide layer; and forming a second oxide layer over the nitride layer.
Claim 8
Dependent Claim
61 words
The method of Claim 1, wherein said second insulating layer forming step comprises the steps of: forming an oxide layer over the integrated circuit; forming a nitride layer over the oxide layer; etching the oxide, nitride, and charge storage capacitor plate layers to define a charge storage node; and forming a second oxide layer over the surface of the integrated circuit.
Claim 9
Dependent Claim
34 words
The method of Claim 8, further comprising the step of: after forming the second oxide layer, anisotropically etching the second oxide layer to form oxide sidewalls on edges of the charge storage node layer.
Claim 10
Dependent Claim
31 words
The method of Claim 1, farther comprising the step of: etching the polycrystalline silicon upper capacitor plate and the polycrystalline silicon lower capacitor plate to define a boundary of the capacitors.
Claim 11
Dependent Claim
94 words
A semiconductor integrated circuit device structure, comprising: a lower polycrystalline silicon capacitor plate; a first insulating layer overlying said lower polycrystalline silicon capacitor plate; a charge storage polycrystalline silicon capacitor plate overlying said first insulating layer and separated from said lower polycrystalline silicon capacitor plate thereby; a second insulating layer overlying said charge storage polycrystalline silicon capacitor plate; and an upper polycrystalline silicon capacitor plate overlying said second insulating layer and separated from said charge storage polycrystalline silicon capacitor plate thereby, wherein said upper capacitor plate is electrically connected to said lower capacitor plate.
Claim 12
Dependent Claim
30 words
The structure of Claim 11, wherein said lower polycrystalline silicon capacitor plate has an opening therein, and said charge storage polycrystalline silicon capacitor plate contacts an active substrate region therethrough.
Claim 13
Dependent Claim
24 words
The device structure of Claim 11, wherein said charge storage polycrystalline silicon capacitor plate is a charge storage node of a DRAM memory cell.
Claim 14
Dependent Claim
24 words
The device structure of Claim 11, wherein said first insulating layer comprises: a first oxide layer; a nitride layer; and a second oxide layer.
Claim 15
Dependent Claim
24 words
The device structure of Claim 11, wherein said second insulating layer comprises: a first oxide layer; a nitride layer; and a second oxide layer.
References Cited (Backward Citations)
US4700457A
Cited
EP0370407A1
Cited
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