High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

Claim 2

A MOS device comprising: an insulating substrate; a silicon layer formed on said insulating substrate wherein said silicon layer is less than approximately 1000Å thick and is substantially free of electrically active states achieved by restricting all processing of said silicon layer to temperatures of less than or equal to approximately 950° C.; a source region formed in said silicon layer; a drain region formed in said silicon layer; a channel region formed in said silicon layer between said source region and said drain region; and a gate positioned adjacent said channel region.

Claim 3

A MOS device as defined in claim 1 wherein said insulating substrate comprises sapphire.

Claim 4

A MOS device as defined in claim 1 wherein said silicon layer has an areal density of electrically active states which is less than approximately 5×10 11 cm -2 .

Claim 5

A MOS device as defined in claim 1 wherein said channel has a length of less than approximately 0.8 μm.

Claim 6

AMOS device as defined in claim 1 wherein said source region and said drain region overlap said gate by less than approximately 0.06 μm.

Claim 7

A NAND gate comprising: an insulating substrate; a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000Å thick and is substantially free of electrically active states achieved by restricting all processing of said layer of silicon to temperatures of less than or equal to approximately 950° C.; first and second P-channel transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second P-channel transistors have widths of less than approximately 1.3 μm and lengths of less than approximately 0.7 μm; a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate wherein said first N-channel transistor has a width of less than approximately 0.9 μm and a length of less than approximately 0.8 μm; and a second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate wherein said second N-channel transistor has a width of less than approximately 1.0 μm and a length of less than approximately 0.8 μm.

Claim 8

A NAND gate comprising: an insulating substrate; a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000Å thick and is substantially free of electrically active states achieved by restricting all processing of said layer of silicon to temperatures of less than or equal to approximately 950° C.; first and second P-channel transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second P-channel transistors have widths of less than approximately 1.3 μm and lengths of less than approximately 0.7 μm; a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate wherein said first N-channel transistor has a width of less than approximately 0.9 μm and a length of less than approximately 0.8 μm; and a second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate wherein said second N-channel transistor has a width of less than approximately 1.0 μm and a length of less than approximately 0.8 μm.

Claim 9

A NOR gate comprising: an insulating substrate; a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000Å thick and is substantially free of electrically active states achieved by restricting all processing of said layer of silicon to temperatures of less than or equal to approximately 950° C.; first and second PMOS transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second PMOS transistors have widths of less than approximately 1.5 μm and lengths of less than approximately 0.7 μm; and first and second NMOS transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second NMOS transistors have widths of less than approximately 1.0 μm and lengths of less than approximately 0.8 μm.

Claim 10

A NOR gate comprising: an insulating substrate; a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000Å thick and is substantially free of electrically active states achieved by restricting all processing of said layer of silicon to temperatures of less than or equal to approximately 950° C.; first and second PMOS transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second PMOS transistors have widths of less than approximately 1.5 μm and lengths of less than approximately 0.7 μm; and first and second NMOS transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second NMOS transistors have widths of less than approximately 1.0 μm and lengths of less than approximately 0.8 μm.

Claim 11

(AMENDED) A MOS device comprising: an insulating substrate; a silicon layer formed on said sapphire substrate wherein said silicon layer is less than approximately 1000Å thick and is substantially free of electrically active states achieved by restricting all processing of said silicon layer to temperatures of less than or equal to approximately 950° C.; a source region formed in said silicon layer, wherein a voltage V S is applied to said source region; a drain region formed in said silicon layer, wherein a voltage V D is applied to said drain region; a channel region formed in said silicon layer between said source region and said drain region; and a gate positioned adjacent said channel region, wherein a voltage V G is applied to said source region to control current flowing between said source and said drain, I DS .

Claim 12

(AMENDED) A MOS device comprising: an insulating substrate; a silicon layer formed on said sapphire substrate wherein said silicon layer is less than approximately 1000Å thick and is substantially free of electrically active states achieved by restricting all processing of said silicon layer to temperatures of less than or equal to approximately 950° C.; a source region formed in said silicon layer, wherein a voltage V S is applied to said source region; a drain region formed in said silicon layer, wherein a voltage V D is applied to said drain region; a channel region formed in said silicon layer between said source region and said drain region; and a gate positioned adjacent said channel region, wherein a voltage V G is applied to said source region to control current flowing between said source and said drain, I DS .

Claim 13

A MOS device as defined in claim 8 wherein said current flowing through said channel from said source to said drain, I DS , is a linear function of the voltage difference between said source and said drain, V D -V S =V DS .

Claim 14

A MOS device as defined in claim 8 wherein said channel is fully depleted.

Claim 15

A digital electronic circuit comprising: an electrically insulating substrate; a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×10 11 cm -2 achieved by restricting all processing of the semiconductive silicon layer to temperatures of less than or equal to approximately 950° C.; and a digital field effect transistor element that is formed in the silicon layer and includes: an N-type source; an N-type drain; and a P-type channel having a gate length of less than approximately 0.8 micrometers, negligible source-body effect and a mobility higher than approximately 180 cm/volt-second; and a gate formed over the channel.

Claim 16

A digital electronic circuit comprising: an electrically insulating substrate; a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×10 11 cm -2 achieved by restricting all processing of the semiconductive silicon layer to temperatures of less than or equal to approximately 950° C.; and a digital field effect transistor element that is formed in the silicon layer and includes: an N-type source; an N-type drain; and a P-type channel having a gate length of less than approximately 0.8 micrometers, negligible source-body effect and a mobility higher than approximately 180 cm/volt-second; and a gate formed over the channel.