US5568065A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for connecting a node to a voltage source selected from alternative voltage sources
Assignee: National Semiconductor Corp
•
Filing: 1995-06-01
•
Granted: 1996-10-22
•
Expires: 2015-06-01
Abstract
Abstract A circuit connects a circuit node to a voltage source selected between two alternative power supply voltage sources. The circuit includes two transistors, specifically a first transistor selectively connecting the circuit node to a first power supply voltage source of the two alternative power supply voltage sources and a second transistor selectively connecting the circuit node to the second power supply voltage source. The first transistor has a gate connected to the second power supply voltage source. The second transistor has a gate connected to the first power supply voltage source. The circuit passes the lowest voltage supplied by the two alternative voltage sources to the circuit node. The circuit is useful, for example, in a voltage translation and overvoltage protection circuit.
Inventors
- 👤 Joseph D. Wert
- 👤 Richard L. Duncan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:10
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/003; H03K19/00315; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
113 words
A circuit for selectively coupling a circuit node to one voltage source of two alternative power supply voltage sources comprising: a first transistor selectively coupling the circuit node to a first power supply voltage source of the two alternative power supply voltage sources, the first transistor having a gate coupled to a second power supply voltage source of the two alternative power supply voltage sources; and a second transistor selectively coupling the circuit node to the second power supply voltage source, the second transistor having a gate coupled to the first power supply voltage source; wherein the circuit passes the lowest voltage supplied by the two alternative voltage sources to the circuit node.
Claim 2
Dependent Claim
113 words
A circuit for selectively coupling a circuit node to one voltage source of two alternative power supply voltage sources comprising: a first transistor selectively coupling the circuit node to a first power supply voltage source of the two alternative power supply voltage sources, the first transistor having a gate coupled to a second power supply voltage source of the two alternative power supply voltage sources; and a second transistor selectively coupling the circuit node to the second power supply voltage source, the second transistor having a gate coupled to the first power supply voltage source; wherein the circuit passes the lowest voltage supplied by the two alternative voltage sources to the circuit node.
Claim 3
Dependent Claim
18 words
A circuit according to claim 1 wherein the first transistor and the second transistor are N-channel MOS transistors.
Claim 4
Dependent Claim
95 words
A circuit for supplying to a node a voltage selected from two alternative power supply voltages, the circuit comprising: a first transistor having a source-drain pathway coupling the node to a first power supply voltage of the two alternative power supply voltages, the first transistor having a gate terminal invariably supplied by a second power supply voltage of the two power supply voltages; and a second transistor having a source-drain pathway coupling the node to the second power supply voltage, the second transistor having a gate terminal invariably supplied by the first power supply voltage.
Claim 5
Dependent Claim
95 words
A circuit for supplying to a node a voltage selected from two alternative power supply voltages, the circuit comprising: a first transistor having a source-drain pathway coupling the node to a first power supply voltage of the two alternative power supply voltages, the first transistor having a gate terminal invariably supplied by a second power supply voltage of the two power supply voltages; and a second transistor having a source-drain pathway coupling the node to the second power supply voltage, the second transistor having a gate terminal invariably supplied by the first power supply voltage.
Claim 6
Dependent Claim
18 words
A circuit according to claim 3 wherein the first transistor and the second transistor are N-channel MOS transistors.
Claim 7
Dependent Claim
23 words
A circuit according to claim 3 wherein the circuit passes the lowest voltage supplied by the two alternative voltage sources to the node.
Claim 8
Dependent Claim
102 words
A circuit comprising: a voltage selection circuit supplying to a node a lower voltage of two alternative power supply voltages, the voltage selection circuit including: a first N-channel transistor having a source-drain pathway coupling the node to a first power supply voltage of the two alternative power supply voltages, the first N-channel transistor having a gate terminal supplied by a second power supply voltage of the two power supply voltages; and a second N-channel transistor having a source-drain pathway coupling the node to the second power supply voltage, the second transistor having a gate terminal supplied by the first power supply voltage.
Claim 9
Dependent Claim
102 words
A circuit comprising: a voltage selection circuit supplying to a node a lower voltage of two alternative power supply voltages, the voltage selection circuit including: a first N-channel transistor having a source-drain pathway coupling the node to a first power supply voltage of the two alternative power supply voltages, the first N-channel transistor having a gate terminal supplied by a second power supply voltage of the two power supply voltages; and a second N-channel transistor having a source-drain pathway coupling the node to the second power supply voltage, the second transistor having a gate terminal supplied by the first power supply voltage.
References Cited (Backward Citations)
US4017830A
Cited
US3949242A
Cited
FR2373921A1
Cited
US4583204A
Cited
US4490633A
Cited
US4574273A
Cited
US4583203A
Cited
US4473758A
Cited
US4556804A
Cited
US4727266A
Cited
US4617473A
Cited
US4638182A
Cited
US4862240A
Cited
US4656373A
Cited
US4864373A
Cited
US4740713A
Cited
US4670668A
Cited
US4670861A
Cited
US4837462A
Cited
US4930112A
Cited
US4906056A
Cited
US5060044A
Cited
US4825275A
Cited
US5087579A
Cited
DE3729951A1
Cited
US4952825A
Cited
US5004936A
Cited
US4961010A
Cited
WO1991008341A1
Cited
US5027008A
Cited
US5036222A
Cited
US5117129A
Cited
US5134316A
Cited
US5128560A
Cited
US5157279A
Cited
US5160855A
Cited
US5191244A
Cited
US5350951A
Cited
US5266849A
Cited
US5381061A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |