US4473758A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Substrate bias control circuit and method
Assignee: Motorola Solutions Inc
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Filing: 1983-02-07
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Granted: 1984-09-25
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Expires: 2003-02-07
Abstract
Abstract An integrated circuit and method includes a substrate bias voltage control circuit formed on a common substrate therewith for ensuring that the substrate has a voltage applied thereto while a semiconductor device on the substrate has a supply voltage applied thereto which includes means for providing sources of bias and supply voltages to the substrate with means for firstly coupling the bias voltage to the substrate when the bias voltage is present and means for secondly coupling the supply voltage to the substrate when the bias voltage is not present.
Inventors
- 👤 Robert C. Huntington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:07
CPC Classifications
H; H03; H03K; H03K3/00; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
84 words
An integrated circuit including a bias voltage control circuit formed on a common substrate therewith for insuring that the substrate has a voltage applied thereto while a semiconductor device on said substrate has a supply voltage applied thereto comprising: means for providing sources of bias and supply voltages of said substrate; first means for coupling said bias voltage to said substrate when said bias voltage is present; and second means for coupling said supply voltage to said substrate when said bias voltage is absent.
Claim 2
Dependent Claim
84 words
An integrated circuit including a bias voltage control circuit formed on a common substrate therewith for insuring that the substrate has a voltage applied thereto while a semiconductor device on said substrate has a supply voltage applied thereto comprising: means for providing sources of bias and supply voltages of said substrate; first means for coupling said bias voltage to said substrate when said bias voltage is present; and second means for coupling said supply voltage to said substrate when said bias voltage is absent.
Claim 3
Dependent Claim
31 words
The integrated circuit of claim 1 wherein said first means for coupling further comprises: means for decoupling said bias voltage providing means from said substrate when said bias voltage is absent.
Claim 4
Dependent Claim
31 words
The integrated circuit of claim 1 wherein said second means for coupling further comprises: means for decoupling said supply voltage providing means from said substrate when said bias voltage is present.
Claim 5
Dependent Claim
14 words
The integrated circuit of claim 1 wherein said semiconductor device comprises a CMOS inverter.
Claim 6
Dependent Claim
19 words
The integrated circuit of claim 1 wherein said bias and supply voltages are substantially 5.0 and 3.0 volts respectively.
Claim 7
Dependent Claim
14 words
The integrated circuit of claim 1 wherein said substrate comprises N type semiconductor material.
Claim 8
Dependent Claim
16 words
The integrated circuit of claim 1 wherein said first and second coupling means comprises MOS transistors.
Claim 9
Dependent Claim
14 words
The integrated circuit of claim 7 wherein said MOS transistors are P channel devices.
Claim 10
Dependent Claim
14 words
The integrated circuit of claim 2 wherein said decoupling means comprises a CMOS inverter.
Claim 11
Independent Claim
70 words
A method for insuring that an integrated circuit substrate has a voltage applied thereto while a semiconductor device on said substrate has a supply voltage applied thereto comprising the steps of: providing sources of bias and supply voltages to said substrate; firstly coupling said bias voltage to said substrate when said bias voltage is present; and secondly coupling said supply voltage to said substrate when said bias voltage is absent.
Claim 12
Independent Claim
70 words
A method for insuring that an integrated circuit substrate has a voltage applied thereto while a semiconductor device on said substrate has a supply voltage applied thereto comprising the steps of: providing sources of bias and supply voltages to said substrate; firstly coupling said bias voltage to said substrate when said bias voltage is present; and secondly coupling said supply voltage to said substrate when said bias voltage is absent.
Claim 13
Dependent Claim
24 words
The method of claim 10 wherein said step of secondly coupling further comprises the step of: decoupling said bias voltage source from said substrate.
Claim 14
Dependent Claim
24 words
The method of claim 10 wherein said step of firstly coupling further comprises the step of: decoupling said supply voltage source from said substrate.
Claim 15
Dependent Claim
29 words
The method of claim 10 wherein said step of providing is carried out by means of a bias voltage of 5.0 volts and a supply voltage of 3.0 volts.
Claim 16
Dependent Claim
21 words
The method of claim 12 wherein said steps of firstly and secondly coupling are carried out by means of MOS transistors.
Claim 17
Dependent Claim
13 words
The method of claim 14 wherein said MOS transistors are P channel devices.
Claim 18
Dependent Claim
23 words
The method of claim 11 wherein said step of decoupling said bias voltage source is carried out by means of a CMOS inverter.
Claim 19
Dependent Claim
118 words
A substrate bias voltage control circuit comprising: first switching means coupling a substrate bias voltage bus to a circuit ground, said first switching means having a first input thereof connected to a supply voltage bus, inverter means connected between said supply voltage bus and said circuit ground, said inverter means having an input node thereof connected to said substrate bias voltage bus and an output node thereof, and second and third switching means coupling said supply and substrate bias voltage buses respectively to a substrate contact point, said second switching means having a second input thereof connected to said substrate bias voltage bus and said third switching means having a third input thereof connected to said output node.
Claim 20
Dependent Claim
118 words
A substrate bias voltage control circuit comprising: first switching means coupling a substrate bias voltage bus to a circuit ground, said first switching means having a first input thereof connected to a supply voltage bus, inverter means connected between said supply voltage bus and said circuit ground, said inverter means having an input node thereof connected to said substrate bias voltage bus and an output node thereof, and second and third switching means coupling said supply and substrate bias voltage buses respectively to a substrate contact point, said second switching means having a second input thereof connected to said substrate bias voltage bus and said third switching means having a third input thereof connected to said output node.
Claim 21
Dependent Claim
20 words
The substrate bias voltage control circuit of claim 17 wherein said first, second and third switching means comprise MOS transistors.
Claim 22
Dependent Claim
36 words
The substrate bias voltage control circuit of claim 18 wherein said first switching means comprises an N channel device, said second and third switching means comprise P-channel devices and said inverter means comprises a CMOS inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1987-09-25 | 1988-03-26 | 1988-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-25 | 1992-03-26 | 1992-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-25 | 1996-03-26 | 1996-09-25 | $7700.00 | Window Closed / Lapsed |