Back gate bias voltage generator circuit

Claim 2

A circuit for providing control of the back bias voltage on semiconductor devices included in a semiconductor substrate including a gate circuit and being characterized in that: the gate circuit (A, 24) comprises two input terminals and an output terminal (16); the first input terminal of the gate circuit (A, 24) is couplable to a first power supply (VCC); the second input terminal of the gate circuit (A, 24) is couplable to the substrate; the output terminal (16) of the gate circuit (A, 24) is couplable to a non-substrate terminal of the devices whose back bias voltage is to be controlled; and further characterized in that when potential levels of the substrate and the first power supply (VCC) are within preselected ranges then the potential of the output terminal (16) of the gate circuit (A, 24) is at a first potential level, and if either or both of the potentials of the power supply (VCC) or the substrate (VSub) are outside of the preselected ranges then the output terminal (16) of the gate circuit (A, 24) changes in potential to a second potential level which is different than the first potential level and which increases the back bias voltage on the semiconductor devices.

Claim 3

The circuit of claim 1 being further characterized by a substrate generator circuit (C) which is formed on the semiconductor substrate and which is couplable to the first power supply and to generate a potential (VSub) which is applied to the substrate.

Claim 4

The circuit of claim 2 characterized in that the gate circuit (A, 24) is a two input NAND logic gate (A, 24).

Claim 5

Circuitry for providing control of the back gate bias voltage of semiconductor devices formed on a common semiconductor substrate including first, second, and third switching devices (Q4, Q5, and Q6) each having a control terminal and a first and second output terminal, first, second, and third load elements (Q1, Q2, and Q3) each having first and second terminals, the first output terminal of the first switching device (Q4) being coupled to the first terminal of the first load element (Q1), and to the control terminal of the second switching device (Q5), and to a first terminal (12), the first output terminal of the second switching device (Q5) being coupled to the control terminal of the third switching device (Q6), and to the first terminal of the second load element (Q2), and to a second terminal (14), the first output terminal of the third switching device (Q6) being coupled to the first terminal of the third load device (Q3), and to a third terminal (16), and being characterized by: voltage limiting means (Q7) coupled to the third circuit terminal (16) which serves as an output terminal; the second terminals of the first and third load elements (Q1, Q3) being coupled together to a fourth terminal (VCCA); the second terminal of the second load element being coupled to a fifth circuit terminal (VCC) which serves as a first input terminal and which is not directly connected to the fourth terminal; the second output terminal of each of the second and third switching devices (Q5, Q6) being coupled together to a sixth terminal (VSS); and the second output terminal of the first switching device (Q4) being coupled to the substrate which serves as a second input terminal.

Claim 6

Circuitry for providing control of the back gate bias voltage of semiconductor devices formed on a common semiconductor substrate including first, second, and third switching devices (Q4, Q5, and Q6) each having a control terminal and a first and second output terminal, first, second, and third load elements (Q1, Q2, and Q3) each having first and second terminals, the first output terminal of the first switching device (Q4) being coupled to the first terminal of the first load element (Q1), and to the control terminal of the second switching device (Q5), and to a first terminal (12), the first output terminal of the second switching device (Q5) being coupled to the control terminal of the third switching device (Q6), and to the first terminal of the second load element (Q2), and to a second terminal (14), the first output terminal of the third switching device (Q6) being coupled to the first terminal of the third load device (Q3), and to a third terminal (16), and being characterized by: voltage limiting means (Q7) coupled to the third circuit terminal (16) which serves as an output terminal; the second terminals of the first and third load elements (Q1, Q3) being coupled together to a fourth terminal (VCCA); the second terminal of the second load element being coupled to a fifth circuit terminal (VCC) which serves as a first input terminal and which is not directly connected to the fourth terminal; the second output terminal of each of the second and third switching devices (Q5, Q6) being coupled together to a sixth terminal (VSS); and the second output terminal of the first switching device (Q4) being coupled to the substrate which serves as a second input terminal.

Claim 7

The circuitry of claim 4 characterized in that the voltage limiting means (Q7) is a fourth switching device having a control terminal and a first output terminal which are both coupled to the third terminal (16) and having a second output terminal which is coupled to the sixth terminal (VSS).

Claim 8

The circuitry of claim 5 characterized in that the first, second, third and fourth switching devices (Q4, Q5, Q6, Q7) are n-channel MOS transistors.

Claim 9

The circuitry of claim 6 characterized in that: the first, second and third load elements (Q1, Q2, Q3), are separate switching devices which each have a control terminal, a first output terminal, and a second output terminal; the control terminal and the first output terminal of the first switching device load element (Q1) being coupled to the first terminal (12); the control terminal and the first output terminal of the second switching device load element (Q2) being coupled to the second terminal (14); and the control terminal and the first output terminal of the third switching device load element (Q3) being coupled to the third terminal (16).

Claim 10

The circuitry of claim 7 characterized in that: the first, second, third, and fourth switching devices (Q4, Q5, Q6, Q7) and the first, second, and third switching device load elements (Q1, Q2, Q3) are first, second, third, fourth, fifth, sixth, and seventh MOS transistors (Q4, Q5, Q6, Q7, Q1, Q2, Q3), respectively.

Claim 11

The circuitry of claim 8 characterized in that: the first, second, third, and fourth MOS transistors (Q4, Q5, Q6, Q7) are enhancement mode n-channel transistors; and the fifth, sixth and seventh MOS transistors (Q1, Q2, Q3) are depletion mode n-channel transistors.