Semiconductor decoder circuit having switching means for preventing counterflow

Claim 2

A semiconductor circuit comprising: a preceding circuit which delivers an output signal of first amplitude in response to an input signal; a power source which has a first potential to be fed to said preceding circuit; a succeeding circuit which includes at least one insulated-gate field effect transistor and to which the output signal of said preceding circuit is applied, said succeeding circuit delivering an output signal of a second amplitude larger than the first amplitude in response to the output signal of said preceding circuit and being supplied with a voltage of a second potential from a second power source higher than the first potential; and a switching means for preventing counterflow of current to the preceding circuit from the succeeding circuit, coupled between the preceding circuit and the succeeding circuit; and wherein said preceding circuit is a decoder circuit which decodes an address signal, and said succeeding circuit is a word line driver which drives a word line of a memory, and said memory is dynamic random access memory.

Claim 3

A semiconductor circuit according to claim 1, wherein: said switching means is MOS transistor in which a source or drain is connected to an output of the preceding circuit, and a drain or source is connected to an input of the succeeding circuit.

Claim 4

A semiconductor circuit comprising: a preceding circuit which delivers an output signal of first amplitude in response to an input signal; a first power source which has a first potential to be fed to said preceding circuit: a succeeding circuit which includes at least one insulated gate field effect transistor and to which the output signal of said preceding circuit is applied, said succeeding circuit delivering an output signal of a second amplitude larger than the first amplitude in response to the output signal of said preceding circuit and being supplied with a voltage of a second potential from a second power source higher than the first potential; and a switching means for preventing counterflow of current to the preceding circuit from the succeeding circuit, coupled between the preceding circuit and the succeeding circuit, and wherein said preceding circuit is constructed of a first p-channel MOSFET and a first n-channel MOSFET, gate electrodes of both said MOSFETs being electrically connected to form an input node to which the input signal is applied; a source or drain electrode of said first p-channel MOSFET is connected to said first power source which has the first potential; the drain or source electrode of said first p-channel MOSFET is connected to a source or drain electrode of said first n-channel MOSFET, to form an output node; the drain or source of said first n-channel MOSFET is connected to a reference potential; said succeeding circuit including a second p-channel MOSFET, a second n-channel MOSFET, a further switching means and a first bipolar transistor; a gate electrode of said second p-channel MOSFET, a gate electrode of said second n-channel MOSFET and a first electrode of said further switching means are electrically connected to form an input node of said succeeding circuit to which the output signal of said preceding circuit is applied; a source or drain electrode of said second p-channel MOSFET is connected to a third power source which has a third potential lower than the second potential; a collector electrode of said first bipolar transistor is electrically connected to the second power source having the second potential; the drain or source electrode of said second p-channel MOSFET, a source or drain electrode of said second n-channel MOSFET and a base electrode of said first bipolar transistor are electrically connected together; the drain or source electrode of said second n-channel MOSFET is connected to the reference potential; an emitter electrode of said first bipolar transistor and a second electrode of said further switching means are electrically connected to form an output node which delivers the signal having the second amplitude; and a third electrode of said further switching means is connected to the reference potential.

Claim 5

A semiconductor circuit comprising: a preceding circuit which delivers an output signal of first amplitude in response to an input signal; a first power source which has a first potential to be fed to said preceding circuit: a succeeding circuit which includes at least one insulated gate field effect transistor and to which the output signal of said preceding circuit is applied, said succeeding circuit delivering an output signal of a second amplitude larger than the first amplitude in response to the output signal of said preceding circuit and being supplied with a voltage of a second potential from a second power source higher than the first potential; and a switching means for preventing counterflow of current to the preceding circuit from the succeeding circuit, coupled between the preceding circuit and the succeeding circuit, and wherein said preceding circuit is constructed of a first p-channel MOSFET and a first n-channel MOSFET, gate electrodes of both said MOSFETs being electrically connected to form an input node to which the input signal is applied; a source or drain electrode of said first p-channel MOSFET is connected to said first power source which has the first potential; the drain or source electrode of said first p-channel MOSFET is connected to a source or drain electrode of said first n-channel MOSFET, to form an output node; the drain or source of said first n-channel MOSFET is connected to a reference potential; said succeeding circuit including a second p-channel MOSFET, a second n-channel MOSFET, a further switching means and a first bipolar transistor; a gate electrode of said second p-channel MOSFET, a gate electrode of said second n-channel MOSFET and a first electrode of said further switching means are electrically connected to form an input node of said succeeding circuit to which the output signal of said preceding circuit is applied; a source or drain electrode of said second p-channel MOSFET is connected to a third power source which has a third potential lower than the second potential; a collector electrode of said first bipolar transistor is electrically connected to the second power source having the second potential; the drain or source electrode of said second p-channel MOSFET, a source or drain electrode of said second n-channel MOSFET and a base electrode of said first bipolar transistor are electrically connected together; the drain or source electrode of said second n-channel MOSFET is connected to the reference potential; an emitter electrode of said first bipolar transistor and a second electrode of said further switching means are electrically connected to form an output node which delivers the signal having the second amplitude; and a third electrode of said further switching means is connected to the reference potential.

Claim 6

A semiconductor circuit comprising: a preceding circuit which delivers an output signal of first amplitude in response to an input signal; a power source which has a first potential to be fed to said preceding circuit; a succeeding inverter circuit which includes at least one insulated-gate field effect transistor and to which the output signal of said preceding circuit is applied, said succeeding inverter circuit delivering an inverted output signal of a second amplitude larger than the first amplitude in response to the output signal of said preceding circuit and being supplied with a voltage of a second potential from a second power source higher than the first potential; a switching means for preventing counterflow of current to the preceding circuit from the succeeding inverter circuit, coupled between an output node of the preceding circuit and an input node of the succeeding inverter circuit; a second switching means coupled between the second power source and the input node of the succeeding inverter circuit, a switching operation of the second switching means is controlled by the inverted output signal of the succeeding inverter circuit; a third switching means coupled between the second power source and the input node of the succeeding inverter circuit, a switching operation of the third switching means is controlled by a control signal; and wherein the control signal causes the third switching means to be in an on state during a predetermined period in response to a change of levels of the output signal of said preceding circuit.

Claim 7

A semiconductor circuit comprising: a preceding circuit which delivers an output signal of first amplitude in response to an input signal; a power source which has a first potential to be fed to said preceding circuit; a succeeding inverter circuit which includes at least one insulated-gate field effect transistor and to which the output signal of said preceding circuit is applied, said succeeding inverter circuit delivering an inverted output signal of a second amplitude larger than the first amplitude in response to the output signal of said preceding circuit and being supplied with a voltage of a second potential from a second power source higher than the first potential; a switching means for preventing counterflow of current to the preceding circuit from the succeeding inverter circuit, coupled between an output node of the preceding circuit and an input node of the succeeding inverter circuit; a second switching means coupled between the second power source and the input node of the succeeding inverter circuit, a switching operation of the second switching means is controlled by the inverted output signal of the succeeding inverter circuit; a third switching means coupled between the second power source and the input node of the succeeding inverter circuit, a switching operation of the third switching means is controlled by a control signal; and wherein the control signal causes the third switching means to be in an on state during a predetermined period in response to a change of levels of the output signal of said preceding circuit.

Claim 8

A semiconductor circuit according to claim 4 wherein: the second switching means is constructed of a second insulated-gate field effect transistor; the third switching means is constructed of a third insulated-gate field effect transistor; and the third insulated-gate field effect transistor has a gate width larger than that of the second insulated-gate field effect transistor.

Claim 9

A semiconductor circuit according to claim 5 wherein: said preceding circuit is a decoder circuit which decodes an address signal, and said succeeding circuit is a word line driver which drives a word line of a memory; and said memory is dynamic random access memory.