← Back to Patent Explorer
US4574273A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit for changing the voltage level of binary signals

Assignee: Toshiba Corp
•
Filing: 1983-11-04
•
Granted: 1986-03-04
•
Expires: 2003-11-04
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A voltage converter circuit has an input terminal for receiving an input binary signal and a gate for generating an output binary signal corresponding to the input binary signal. An output signal from the gate is supplied to a first input terminal of an inverter through a transistor and further to a second input terminal of the inverter directly, so as to immediately stabilize the output signal from the voltage converter circuit. The inverter inverts the input signal to a higher-voltage binary signal. When a voltage level of the higher-voltage binary signal reaches a given voltage level while the voltage level of the higher-voltage binary signal changes, a feedback circuit is operated to set the input signal supplied to the first input terminal of the inverter at a higher voltage.

Inventors

  • 👤 Shigeru Atsumi
  • 👤 Sumio Tanaka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 00:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 294 words
A circuit for changing a signal voltage level, comprising: input means for receiving an input binary signal; gate means, connected to said input means, for generating an output binary signal corresponding to the input binary signal; a first reference terminal to which a high voltage, higher than the high level of said input binary signal, is supplied; a second reference terminal to which a constant voltage lower than the high voltage and equal to or higher than the high level of said input binary signal is supplied; a disconnecting n-channel MOS transistor having a current path with two ends, one end of which is connected to said gate means, and a gate which is connected to said second reference terminal; inverting means, having a first input terminal which is connected to the other end of the current path of said disconnecting n-channel MOS transistor and a second input terminal which is connected to said gate means, for converting the output binary signal of said gate means to a higher-volage binary signal, said inverting means having an output terminal for providing the converted higher-voltage binary signal; and feedback means, comprising a p-channel MOS transistor having a source connected to the first reference terminal, a drain connected to said first input terminal of said inverting means, and a gate connected to said output terminal of said inverting means, for causing the voltage level at said first input terminal of said inverting means to be set at said high voltage when the voltage of the converted higher-voltage binary signal reaches a given voltage level, said disconnecting n-channel MOS transistor electrically isolating said gate means and said second input terminal of said inverting means from the high voltage applied at said first input terminal of said inverting means.
Claim 2
Dependent Claim 294 words
A circuit for changing a signal voltage level, comprising: input means for receiving an input binary signal; gate means, connected to said input means, for generating an output binary signal corresponding to the input binary signal; a first reference terminal to which a high voltage, higher than the high level of said input binary signal, is supplied; a second reference terminal to which a constant voltage lower than the high voltage and equal to or higher than the high level of said input binary signal is supplied; a disconnecting n-channel MOS transistor having a current path with two ends, one end of which is connected to said gate means, and a gate which is connected to said second reference terminal; inverting means, having a first input terminal which is connected to the other end of the current path of said disconnecting n-channel MOS transistor and a second input terminal which is connected to said gate means, for converting the output binary signal of said gate means to a higher-volage binary signal, said inverting means having an output terminal for providing the converted higher-voltage binary signal; and feedback means, comprising a p-channel MOS transistor having a source connected to the first reference terminal, a drain connected to said first input terminal of said inverting means, and a gate connected to said output terminal of said inverting means, for causing the voltage level at said first input terminal of said inverting means to be set at said high voltage when the voltage of the converted higher-voltage binary signal reaches a given voltage level, said disconnecting n-channel MOS transistor electrically isolating said gate means and said second input terminal of said inverting means from the high voltage applied at said first input terminal of said inverting means.
Claim 3
Dependent Claim 13 words
A circuit according to claim 1, wherein said gate means comprises an inverter.
Claim 4
Dependent Claim 76 words
A circuit according to claim 1, wherein said inverting means comprises: a p-channel MOS transistor having a source connected to the first reference terminal, a drain connected to said output terminal, and a gate connected to said first input terminal; and an n-channel MOS transistor having a drain connected to said output terminal, a source connected to a terminal to which a ground level voltage is applied, and a gate connected to said second input terminal.

References Cited (Backward Citations)

US3675144A Cited
US3728556A Cited
US4216390A Cited
US4506164A Cited
US4490633A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-03-03 1989-09-02 1990-03-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-03-03 1993-09-02 1994-03-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-03-03 1997-09-02 1998-03-04 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag