Write circuit for use in semiconductor storage device

Claim 2

A write circuit for a semiconductor storage device, said write circuit comprising a data output stage constructed by a composite circuit including: an output circuit including a pair of first and second bipolar transistors, each having a collector, a base, and an emitter, wherein collector-emitter current paths of said pair of bipolar transistors are connected in series to each other between first and second electric potentials, and wherein a connection node of said collector-emitter current paths provides an output of the composite circuit; and an input circuit including a MOS transistor which is responsive to a predetermined input to output a signal for rendering said first bipolar transistor in the on or off state, and wherein said input circuit is further responsive to said predetermined input to output another signal for rendering said second bipolar transistor in the on or off state in an opposite relation to the on-off state of said first bipolar transistor.

Claim 3

A write circuit for a semiconductor storage device according to claim 1, in which said input circuit further includes another MOS transistor responsive to said predetermined input to output another signal for rendering said second bipolar transistor in the on or off state in an opposite relation to the on-off state of said first bipolar transistor.

Claim 4

A write circuit for a semiconductor storage device, said write circuit comprising a data output stage constructed by a composite circuit including: an output circuit including a pair of first and second bipolar transistors, each having a collector, a base, and an emitter, and wherein collector-emitter current paths of said pair of bipolar transistors are connected in series to each other between first and second electric potentials, and wherein a connection node of said collector-emitter current paths provides an output of the composite circuit; and an input circuit including a MOS transistor, wherein said circuit is responsive to a predetermined input to output a signal for rendering said first bipolar transistor in the on or off state, and further wherein said MOS transistor is further responsive to said predetermined input to output another signal for rendering said second bipolar transistor in the on or off state in an opposite relation to the on-off state of said first bipolar transistor.

Claim 5

A write circuit for a semiconductor storage device, said write circuit comprising a data output stage constructed by a composite circuit including: an output circuit including a pair of first and second bipolar transistors, each having a collector, a base, and an emitter, and wherein collector-emitter current paths of said pair of bipolar transistors are connected in series to each other between first and second electric potentials, and wherein a connection node of said collector-emitter current paths provides an output of the composite circuit; and an input circuit including a MOS transistor, wherein said circuit is responsive to a predetermined input to output a signal for rendering said first bipolar transistor in the on or off state, and further wherein said MOS transistor is further responsive to said predetermined input to output another signal for rendering said second bipolar transistor in the on or off state in an opposite relation to the on-off state of said first bipolar transistor.

Claim 6

A write circuit for a semiconductor storage device according to claim 3, in which said input circuit further includes another MOS transistor responsive to said predetermined input to output said signal for rendering said first bipolar transistor in the on or off state.

Claim 7

A write circuit for a semiconductor storage device, comprising: a data output stage constructed by a composite circuit including an output circuit including a bipolar transistor having a collector, a base, and an emitter, and wherein either of said collector and said emitter provides an output of the composite circuit; an input circuit including a MOS transistor which is responsive to a predetermined input to output a signal for rendering said bipolar transistor in the on or off state; and means for preventing the saturation of a sense circuit which is coupled to sense an output from said semiconductor storage device.

Claim 8

A write circuit for a semiconductor storage device, comprising: a data output stage constructed by a composite circuit including an output circuit including a bipolar transistor having a collector, a base, and an emitter, and wherein either of said collector and said emitter provides an output of the composite circuit; an input circuit including a MOS transistor which is responsive to a predetermined input to output a signal for rendering said bipolar transistor in the on or off state; and means for preventing the saturation of a sense circuit which is coupled to sense an output from said semiconductor storage device.

Claim 9

A write circuit for a semiconductor storage device according to claim 1, in which said composite circuit further comprises: said pair of first and second bipolar transistors each having a collector of the first conductivity type, a base of the second conductivity type, and an emitter of the first conductivity type; and said input circuit including: a first MOS transistor having a channel of the second conductivity type responsive to said predetermined input for forming a current path from said first potential to the base of said first bipolar transistor to output said signal for rendering said first bipolar transistor in the on or off state, and a second MOS transistor having a channel of the first conductivity type responsive to said predetermined input for forming a current path from at least said output of the composite circuit to the base of said second bipolar transistor to output another signal for rendering said second bipolar transistor in the on or off state in an opposite relation to the on-off state of said first bipolar transistor.

Claim 10

A write circuit for a semiconductor storage device according to claim 1, in which said composite circuit further comprises: a first discharge means for discharging accumulated charges from at least said first bipolar transistor to said second potential, when said first bipolar transistor is switched from the on-state to the off-state; and a second discharge means for discharging accumulated charges from at least said second bipolar transistor to said second potential when said second bipolar transistor is switched from the on-state to the off-state.

Claim 11

A write circuit for a semiconductor storage device according to claim 7, in which said first discharge means includes a third MOS transistor having a channel of the first conductivity type responsive to said predetermined input for forming a current path from the base of said first bipolar transistor to said second potential.

Claim 12

A write circuit for a semiconductor storage device according to claim 7, in which said second discharge means includes a fourth MOS transistor having a channel of the first conductivity type switched into an on state when said first bipolar transistor is on, for forming a current path from the base of said second bipolar transistor to said second potential, and switched into an off state when said first bipolar transistor is off.

Claim 13

A write circuit for a semiconductor storage device according to claim 9, in which said fourth MOS transistor has its gate connected to said output of the composite circuit, and its drain and source connected to the base of said second bipolar transistor and said second potential.

Claim 14

A write circuit for a semiconductor storage device according to claim 6, in which said composite circuit further comprises a unidirectional element for forming a current path from said output of the composite circuit to the base of said second bipolar transistor through said second MOS transistor, and for blocking a current path from the base of said first bipolar transistor to said output of the composite circuit.

Claim 15

A write circuit for a semiconductor storage device according to claim 11, in which said unidirectional element is a diode with the anode thereof connected to said output of the composite circuit, and the cathode thereof connected to the base of said first bipolar transistor.

Claim 16

A write circuit for a semiconductor storage device according to claim 1, in which said emitter of said first bipolar transistor is connected with said output of the composite circuit through a diode.

Claim 17

A write circuit for a semiconductor storage device according to claim 10, in which the gate of said fourth MOS transistor is connected to said output of the composite circuit through a diode.

Claim 18

A write circuit for a semiconductor storage device according to claim 3, in which said composite circuit further comprises: said pair of first and second bipolar transistors each having a collector of the first conductivity type, a base of the second conductivity type, and an emitter of the first conductivity type; and said input circuit including: a first MOS transistor having a channel of the second conductivity type responsive to said predetermined input for forming a current path from said first potential to the base of said first bipolar transistor to output said signal for rendering said first bipolar transistor in the on or off state, and a second MOS transistor having a channel of the first conductivity type responsive to said predetermined input for forming a current path from at least said output of the composite circuit to the base of said second bipolar transistor to output another signal for rendering said second bipolar transistor in the on or off state in an opposite relation to the on-off state of said first bipolar transistor.

Claim 19

A write circuit for a semiconductor storage device according to claim 3, in which said composite circuit further comprises: a first discharge means for discharging accumulated charges from at least said first bipolar transistor to said second potential, when said first bipolar transistor is switched from the on-state to the off-state; and a second discharge means for discharging accumulated charges from at least said second bipolar transistor to said second potential when said second bipolar transistor is switched from the on-state to the off-state.

Claim 20

A write circuit for a semiconductor storage device according to claim 16, in which said first discharge means includes a third MOS transistor having a channel of the first conductivity type responsive to said predetermined input for forming a current path from the base of said first bipolar transistor to said second potential.

Claim 21

A write circuit for a semiconductor storage device according to claim 16, in which said second discharge means includes a fourth MOS transistor having a channel of the first conductivity type switched into an on state when said first bipolar transistor is on, for forming a current path from the base of said second bipolar transistor to said second potential, and switched into an off state when said first bipolar transistor is off.

Claim 22

A write circuit for a semiconductor storage device according to claim 18, in which said fourth MOS transistor has its gate connected to said output of the composite circuit, and its drain and source connected to the base of said second bipolar transistor and said second potential.

Claim 23

A write circuit for a semiconductor storage device according to claim 15, in which said composite circuit further comprises a unidirectional element for forming a current path from said output of the composite circuit to the base of said second bipolar transistor through said second MOS transistor, and for blocking a current path from the base of said first bipolar transistor to said output of the composite circuit.

Claim 24

A write circuit for a semiconductor storage device according to claim 20, in which said unidirectional element is a diode with the anode thereof connected to said output of the composite circuit, and the cathode thereof connected to the base of said first bipolar transistor.

Claim 25

A write circuit for a semiconductor storage device according to claim 3, in which said emitter of said first bipolar transistor is connected with said output of the composite circuit through a diode.

Claim 26

A write circuit for a semiconductor storage device according to claim 19, in which the gate of said fourth MOS transistor is connected to said output of the composite circuit through a diode.