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JPS5658193A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: NEC Corp
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Filing: 1979-10-16
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Granted: —
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Expires: 1999-10-16
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Abstract

Abstract PURPOSE:To form the memory cell consisting of the flip-flop with the MIS-T and other peripheral circuits with the bipolar transistors respectively, thus realizing a large-capacity and high-speed semiconductor memory device having the merits of the memory cell and the peripheral circuit. CONSTITUTION:The memory cells C11, C12, C21 and C22 consisting of the flip-flop in which the gate and the drain of the MIS-T are connected in cross to each other are arranged in the directions of the word and the digit each. Thus a cell matrix is obtained. The digit drivers D11 and D12 are formed with the bipolar transistors. Then the digit lines D1 and D2 are connected to the emitters of the transistors QWC1 and QWC1' receiving the control lines WC and WC from the write/read circuit B at the base plus the transistors QD1 and QD1' receiving the digit selection signal DS1 at the base each. Thus the driving is possible for the digit line of a large capacity. The reading data is sensed by the sense amplifier A.

Inventors

  • 👤 Joji Nokubo

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 05:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412

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