US4646124A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Level shifting BIMOS integrated circuit
Assignee: Allegro Microsystems LLC
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Filing: 1984-07-30
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Granted: 1987-02-24
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Expires: 2004-07-30
Abstract
Abstract An integrated circuit has small signal MOS logic transistors formed in an N-type basket which basket itself is formed in an N-type epitaxial pocket that is defined by an enclosing P-type isolation wall. In a second epitaxial pocket a relatively high-current carrying bipolar transistor is formed. The MOS containing N-type basket is tied to one DC voltage which the substrate and isolation walls are connected to a lower level DC voltage. Substrate currents that are caused by the high current in the bipolar transistor are prevented by the N-type basket from inducing voltage changes in the MOS transistors.
Inventors
- 👤 Michael J. Zunino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:37
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/567; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
262 words
A level shifting BIMOS integrated circuit comprising a silicon substrate of P-type, an N-type epitaxial layer having been grown on a face of said substrate, electrical components formed in said epitaxial layer including a complementary pair of MOS transistors and at least one bipolar transistor, said pair of MOS transistors being formed in a first pocket of said epitaxial layer and said bipolar transistor being formed in a second pocket of said epitaxial layer, a system of P-type isolation walls extending from the surface of and through said epitaxial layer to said P-type substrate and surrounding and defining said epitaxial pockets, an N-type basket in said first pocket comprised of an N-type buried layer formed at said substrate face and partially into said first pocket under said pair of MOS transistors and an N-type plug at least partially around said pair of transistors extending downward through epitaxial layer to said N-type buried layer, the N-channel transistor of said MOS pair including a P-type well region extending from the outer surface of and through said epitaxial layer to said N-type buried layer so that said N-type buried layer is located between said P-type well region and said P-type substrate to electrically isolate one from the other; and a plurality of conductive members overlying said epitaxial layer, one of said conductive members contacting said N-type plug and being adapted for connection to one source of DC voltage, and another and separate of said conductive members contacting said system of P-type isolation walls and being adapted for connection to a source of another DC voltage.
Claim 2
Dependent Claim
262 words
A level shifting BIMOS integrated circuit comprising a silicon substrate of P-type, an N-type epitaxial layer having been grown on a face of said substrate, electrical components formed in said epitaxial layer including a complementary pair of MOS transistors and at least one bipolar transistor, said pair of MOS transistors being formed in a first pocket of said epitaxial layer and said bipolar transistor being formed in a second pocket of said epitaxial layer, a system of P-type isolation walls extending from the surface of and through said epitaxial layer to said P-type substrate and surrounding and defining said epitaxial pockets, an N-type basket in said first pocket comprised of an N-type buried layer formed at said substrate face and partially into said first pocket under said pair of MOS transistors and an N-type plug at least partially around said pair of transistors extending downward through epitaxial layer to said N-type buried layer, the N-channel transistor of said MOS pair including a P-type well region extending from the outer surface of and through said epitaxial layer to said N-type buried layer so that said N-type buried layer is located between said P-type well region and said P-type substrate to electrically isolate one from the other; and a plurality of conductive members overlying said epitaxial layer, one of said conductive members contacting said N-type plug and being adapted for connection to one source of DC voltage, and another and separate of said conductive members contacting said system of P-type isolation walls and being adapted for connection to a source of another DC voltage.
Claim 3
Dependent Claim
50 words
The integrated circuit of claim 1 wherein said P-type well is comprised of a buried P-type region extending upward out of said first N-type buried layer into said first epitaxial pocket and a downward diffused P-type region extending downward into said first epitaxial pocket to overlap said buried P-type region.
Claim 4
Dependent Claim
59 words
The integrated circuit of claim 2 wherein said isolation walls are comprised of a downward diffused P-type portion having the same impurity concentration and depth as that of said downward diffused P-type region in said well, and a buried P-type portion extending upward into said epitaxial layer from said face the same distance as does said P-type buried region.
Claim 5
Dependent Claim
43 words
The integrated circuit of claim 1 wherein said N-type plug is formed completely and continuously around and enclosing said pair of MOS transistors and extends downward everywhere to said N-type buried layer so that said basket is complete and without holes or gaps.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-23 | 1990-08-25 | 1991-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-23 | 1994-08-25 | 1995-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-23 | 1998-08-25 | 1999-02-24 | $7700.00 | Window Closed / Lapsed |