US4225877A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with C-Mos logic, and a bipolar driver with polysilicon resistors
Assignee: Allegro Microsystems LLC
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Filing: 1978-09-05
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Granted: 1980-09-30
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Expires: 1998-09-05
Abstract
Abstract An integrated circuit includes MOS transistors and bipolar transistors, each of both polarity types, in a silicon wafer. High value polysilicon resistors are formed over an outer protective silicon dioxide layer of the silicon wafer, which resistors are rendered conductive by having ion implanted impurities concentrated near the outer surface of the polysilicon body, permitting achievement of close tolerance resistors. The process for making the integrated circuit includes forming a sheet of polysilicon over the entire wafer surface, performing the ion implantation and etching away all but the desired resistor portions of the polysilicon. It also includes heating the wafer to simultaneously anneal the ion implanted polysilicon, form the gate oxide, thicken the oxide over the emitters, and cover the resistor body with a thin protective oxide film.
Inventors
- 👤 Steven W. Miles
- 👤 Paul R. Emerald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:32
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K5/00; H03K5/01; H03K5/02; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/0165; H10D84/0193; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D88/00; H10P; H10P32/00; H10P32/30; H10P32/302; H10P95/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
250 words
An integrated logic-controlled driver circuit comprising a silicon crystal wafer of P-type; and N-type epitaxial layer having been grown on a face of said wafer; electrical components being formed in said epitaxial layer and including a complimentary pair of MOS transistors, a PNP and an NPN transistor; an insulative film on the surface of said epitaxial layer; a polysilicon resistor formed over said insulative film, said PNP transistor, NPN transistor and pair of MOS transistors being in three pockets of said epitaxial layer, respectively, that are electrically isolated from one another, the N-channel transistor of said MOS pair including a P-type well region extending completely through said epitaxial layer, said N-channel transistor further including a shallow heavily doped annular surface region of P-type at the interface between said well region and the surrounding of said N-type epitaxial layer, the P-channel transistor of said MOS pair having spaced P-type source and drain regions at said surface, said PNP transistor having at said surface a P-type emitter region and spaced outwardly therefrom an annular P-type collector region, said NPN transistor having at said surface a P-type base region and an N-type emitter region formed therein, said resistor being comprised of a polysilicon layer containing ion implanted impurities extending from the outer surface thereof substantially only part way through said polysilicon layer, and said PNP and NPN transistors and said resistor comprising a high voltage driver portion, and said N-channel and P-channel transistors comprising a logic portion, respectively, of said logic-controlled driver circuit.
Claim 2
Dependent Claim
250 words
An integrated logic-controlled driver circuit comprising a silicon crystal wafer of P-type; and N-type epitaxial layer having been grown on a face of said wafer; electrical components being formed in said epitaxial layer and including a complimentary pair of MOS transistors, a PNP and an NPN transistor; an insulative film on the surface of said epitaxial layer; a polysilicon resistor formed over said insulative film, said PNP transistor, NPN transistor and pair of MOS transistors being in three pockets of said epitaxial layer, respectively, that are electrically isolated from one another, the N-channel transistor of said MOS pair including a P-type well region extending completely through said epitaxial layer, said N-channel transistor further including a shallow heavily doped annular surface region of P-type at the interface between said well region and the surrounding of said N-type epitaxial layer, the P-channel transistor of said MOS pair having spaced P-type source and drain regions at said surface, said PNP transistor having at said surface a P-type emitter region and spaced outwardly therefrom an annular P-type collector region, said NPN transistor having at said surface a P-type base region and an N-type emitter region formed therein, said resistor being comprised of a polysilicon layer containing ion implanted impurities extending from the outer surface thereof substantially only part way through said polysilicon layer, and said PNP and NPN transistors and said resistor comprising a high voltage driver portion, and said N-channel and P-channel transistors comprising a logic portion, respectively, of said logic-controlled driver circuit.
Claim 3
Dependent Claim
52 words
The integrated circuit of claim 1 wherein said insulative film is a silicon dioxide film, and additionally comprising a silicon dioxide film over said resistor body having the same thickness as that portion of said silicon doxide film which covers the channel regions between the sources and drains of said MOS transistors.
Claim 4
Dependent Claim
24 words
The integrated circuit of claim 1 additionally comprising P-type isolation walls extending through said epitaxial layer to provide said electrical isolation between said pockets.
Claim 5
Dependent Claim
58 words
The integrated circuit of claim 3 wherein said walls are comprised of a buried layer portion extending upward from said wafer partway through said epitaxial layer, a downward portion extending from said epitaxial surface part way through said epitaxial layer and overlapping said buried layer portion, and a shallow contact portion at said surface overlapping said downward portion.
Claim 6
Dependent Claim
66 words
The integrated circuit of claim 4 wherein said P-type well is comprised of a buried layer portion of the same upward extension into said epitaxial layer and the same concentration of P-type impurities as that of said buried layer isolation wall portion; and a downward portion having the same downward extension and the same concentration of P-type impurities as that of said downward diffused wall portion.
Claim 7
Dependent Claim
56 words
The integrated circuit of claim 3 wherein said base region of said NPN transistor, said emitter and said collector of said PNP transistor and said annular well-epitaxial layer interface region of said N-channel transistor have the same downward extensions and the same P-type impurity concentrations as that of said shallow contact portion of said isolation wall.
Claim 8
Dependent Claim
53 words
The integrated circuit of claim 1 wherein said PNP transistor, NPN transistor and polysilicon resistor are connected to form a standard power driver circuit and said MOS transistors are connected to form a standard C-MOS logic switching circuit, the output of said C-MOS circuit being connected to the input of said driver circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-30 | 1984-03-31 | 1984-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-30 | 1988-03-31 | 1988-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-30 | 1992-03-31 | 1992-09-30 | $7700.00 | Window Closed / Lapsed |