High speed booster circuit

Claim 2

A high speed booster circuit having a first power supply set at a first voltage level, a second power supply set at a second voltage level which is higher than said first voltage level, a third power supply set at a third voltage level which is higher than said second voltage level, an input signal line and an output signal line wherein the voltage level of said output signal line is raised at high speed to approximately the same level as said third voltage level, comprising: a first booster circuit including a boost capacitor controlled by said input signal for providing a low impedance connection of said output signal line to said second power supply; and a driver circuit including a second booster circuit responsive to a signal appearing at a terminal of said boost capacitor for providing a low impedance connection of said output signal line to said third power supply and interrupting said low impedance connection of said first booster circuit.

Claim 3

A high speed booster circuit according to claim 1, wherein said third power supply is an internal power supply.

Claim 4

A high speed booster circuit according to claim 2, wherein the output voltage of said third power supply is provided by boosting the voltage of said second power supply.

Claim 5

A high speed booster circuit having a first power supply set at a first voltage level, a second power supply set at a second voltage level which is higher than said first voltage level, a third power supply set at a third voltage level which is higher than said second voltage level, an input signal line and an output signal line wherein the voltage level of said output signal lines is raised at high speed to approximately the same level as said third voltage level, comprising: a first booster circuit including a boost capacitor controlled by said input signal for providing a low impedance connection of said output signal line to said second power supply; and a driver circuit including a second booster circuit responsive to a signal appearing at a terminal of said boost capacitor for providing a low impedance connection of said output signal line to said third power supply and interrupting said low impedance connection of said first booster circuit, wherein said first booster circuit comprises: a first voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage and providing at least said second voltage level in response to an occurrence of said input signal; and a first transistor interposed between said second power supply and said output signal line which is controlled by the output voltage of said first voltage generation circuit; and said second booster circuit comprises: a second voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage having a level higher than said second voltage level with a slight delay from the generation of the voltage in said first voltage generation circuit; and a second transistor interposed between said third power supply and said output signal line which is controlled by the output voltage of the second voltage generation circuit.

Claim 6

A high speed booster circuit having a first power supply set at a first voltage level, a second power supply set at a second voltage level which is higher than said first voltage level, a third power supply set at a third voltage level which is higher than said second voltage level, an input signal line and an output signal line wherein the voltage level of said output signal lines is raised at high speed to approximately the same level as said third voltage level, comprising: a first booster circuit including a boost capacitor controlled by said input signal for providing a low impedance connection of said output signal line to said second power supply; and a driver circuit including a second booster circuit responsive to a signal appearing at a terminal of said boost capacitor for providing a low impedance connection of said output signal line to said third power supply and interrupting said low impedance connection of said first booster circuit, wherein said first booster circuit comprises: a first voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage and providing at least said second voltage level in response to an occurrence of said input signal; and a first transistor interposed between said second power supply and said output signal line which is controlled by the output voltage of said first voltage generation circuit; and said second booster circuit comprises: a second voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage having a level higher than said second voltage level with a slight delay from the generation of the voltage in said first voltage generation circuit; and a second transistor interposed between said third power supply and said output signal line which is controlled by the output voltage of the second voltage generation circuit.

Claim 7

A high speed booster circuit according to claim 4, wherein said first voltage generation circuit generates two kinds of voltages in which a first voltage is approximately the same as said second voltage level and a second voltage is higher than said second voltage level; said first transistor is controlled by said second voltage; and said second voltage generation circuit operates in response to said first voltage.

Claim 8

A high speed booster circuit according to claim 4, wherein said second voltage generation circuit operates in response to the increase of the voltage of said output signal.

Claim 9

A high-speed booster circuit according to claim 4 further including transistor switches for selectively coupling each terminal of said capacitor to each of said first and second power supplies, the improvement comprising: a further transistor including within said first booster circuit for controlling at least one of said transistor switches, said transistor having conduction terminals connected between a second power supply and a control electrode of said at least one of said transistor switches for supplying a charge from said second power supply to one electrode of said capacitor in response to said precharge signal applied to a control electrode of said transistor.

Claim 10

In a high-speed voltage booster circuit of a type having a bootstrap circuit and a driver circuit for use with a semiconductor integrated circuit, at least said driver circuit having a capacitor, the improvement comprising a circuit interposed between said bootstrap circuit and said driver circuit comprising a first transistor and a second transistor connected with series between first and second power supplies, a node between said first and second transistors being connected to an input of said driver circuit, said first transistor having a control electrode connected to a first electrode of said capacitor of said driver circuit and said second transistor having a control electrode connected to an input of said bootstrap circuit.

Claim 11

In a high-speed voltage booster circuit of a type having a bootstrap circuit and a driver circuit for use with a semiconductor integrated circuit, at least said driver circuit having a capacitor, the improvement comprising a circuit interposed between said bootstrap circuit and said driver circuit comprising a first transistor and a second transistor connected with series between first and second power supplies, a node between said first and second transistors being connected to an input of said driver circuit, said first transistor having a control electrode connected to a first electrode of said capacitor of said driver circuit and said second transistor having a control electrode connected to an input of said bootstrap circuit.

Claim 12

In a high-speed booster circuit according to claim 8 further including transistor switches for selectively coupling each terminal of said capacitor to each of said first and second power supplies, the improvement further comprising: a further transistor including within said bootstrap circuit for controlling at least one of said transistor switches, said transistor having conduction terminals connected between a second power supply and a control electrode of said at least one of said transistor switches for supplying a charge from said second power supply to one electrode of said capacitor in response to said precharge signal applied to a control electrode of said transistor.

Claim 13

A high speed booster circuit having a first power supply set at a first voltage level, a second power supply set at a second voltage level which is higher than said first voltage level, a third power supply set at a third voltage level which is higher than said second voltage level, an input signal line and an output signal line wherein the voltage level of said output signal lines is raised at high speed to approximately the same level as said third voltage level, comprising: a first booster circuit including a boost capacitor controlled by said input signal for providing a low impedance connection of said output signal line to said second power supply; and a driver circuit including a second booster circuit responsive to a signal appearing at a terminal of said boost capacitor for providing a low impedance connection of said output signal line to said third power supply and interrupting said low impedance connection of said first booster circuit, wherein said first booster circuit comprises: a first voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage and providing at least said second voltage level in response to an occurrence of said input signal; and a first transistor interposed between said second power supply and said output signal line which is controlled by the output voltage of said first voltage generation circuit; and said second booster circuit comprises: a second voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage having a level higher than said second voltage level with a slight delay from the generation of the voltage in said first voltage generation circuit; and a second transistor interposed between said third power supply and said output signal line which is controlled by the output voltage of the second voltage generation circuit, further comprising a third transistor for discharge interposed between the gate of said first transistor and said first power supply and responsive to the output of said second voltage generation circuit generating a level higher than said second voltage level.

Claim 14

A high speed booster circuit having a first power supply set at a first voltage level, a second power supply set at a second voltage level which is higher than said first voltage level, a third power supply set at a third voltage level which is higher than said second voltage level, an input signal line and an output signal line wherein the voltage level of said output signal lines is raised at high speed to approximately the same level as said third voltage level, comprising: a first booster circuit including a boost capacitor controlled by said input signal for providing a low impedance connection of said output signal line to said second power supply; and a driver circuit including a second booster circuit responsive to a signal appearing at a terminal of said boost capacitor for providing a low impedance connection of said output signal line to said third power supply and interrupting said low impedance connection of said first booster circuit, wherein said first booster circuit comprises: a first voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage and providing at least said second voltage level in response to an occurrence of said input signal; and a first transistor interposed between said second power supply and said output signal line which is controlled by the output voltage of said first voltage generation circuit; and said second booster circuit comprises: a second voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage having a level higher than said second voltage level with a slight delay from the generation of the voltage in said first voltage generation circuit; and a second transistor interposed between said third power supply and said output signal line which is controlled by the output voltage of the second voltage generation circuit, further comprising a third transistor for discharge interposed between the gate of said first transistor and said first power supply and responsive to the output of said second voltage generation circuit generating a level higher than said second voltage level.