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US3889135A
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Bootstrap circuit employing insulated gate transistors
Assignee: Hitachi Ltd
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Filing: 1973-06-28
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Granted: 1975-06-10
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Expires: 1993-06-28
Abstract
Abstract A bootstrap circuit employing insulated gate transistors comprises a load element connected at one end to a voltage source, an insulated gate transistor connected between the other end of the load element and ground, a load element connected between the voltage source and a gate electrode of an insulated gate transistor at the following stage, and a capacitor connected between the juncture of the first-mentioned load and the firstmentioned transistor. A clock pulse is applied to a gate electrode of the first-mentioned transistor, so that the output potential of a push-pull buffer circuit, for example, which includes the bootstrap circuit may be held high without being severely subjected to the condition that the output impedance of the clock pulse source be low.
Inventors
- 👤 Kosei Nomiya
- 👤 Yoshikazu Hatsukano
- 👤 Kazuo Minorikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:11
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
378 words
A bootstrap circuit employing insulated gate field effect transistors comprising: a first insulated gate field effect transistor having a source, a drain, and a gate electrode; first means for coupling the drain electrode of said first transistor to a first power source; a second insulated gate field effect transistor having a source, a drain, and a gate electrode; a first capacitor connected between the drain electrode of said second transistor and the gate electrode of said first transistor; second means for coupling the source electrode of said second transistor to a source of reference potential; third means for coupling a first clock pulse to the gate electrode of said second transistor; a first impedance coupled between said first means and the drain electrode of said second transistor; a second impedance coupled between said first means and the gate electrode of said first transistor; a third insulated gate field effect transistor having a source, a drain and a gate electrode, the drain and source electrodes of whIch being respectively connected to the source electrode of said first insulated gate field effect transistor and said source of reference potential; an inverter means including a fourth and a fifth insulated gate field effect transistor connected in series between a second power source and said source of reference potential, the gate electrode of said fourth insulated gate field effect transistor being connected to the source electrode of said first insulated gate field effect transistor, and the gate electrodes of said third and fifth insulated gate field effect transistors being connected together to an input signal terminal; an output means for deriving an output from said inverter means connected to the source electrode of said fourth insulating gate field effect transistor; and further including a sixth insulated gate field effect transistor having a source, a drain and a gate electrode, the source electrode of which is connected to said second means, a second capacitor connected between the source electrode of said first transistor and the drain electrode of said sixth transistor, a third impedance connected between said first means and the drain electrode of said sixth transistor, and fourth means for coupling a second clock pulse, shifted in time relative to said first clock pulse, to the gate electrode of said sixth transistor.
Claim 2
Dependent Claim
378 words
A bootstrap circuit employing insulated gate field effect transistors comprising: a first insulated gate field effect transistor having a source, a drain, and a gate electrode; first means for coupling the drain electrode of said first transistor to a first power source; a second insulated gate field effect transistor having a source, a drain, and a gate electrode; a first capacitor connected between the drain electrode of said second transistor and the gate electrode of said first transistor; second means for coupling the source electrode of said second transistor to a source of reference potential; third means for coupling a first clock pulse to the gate electrode of said second transistor; a first impedance coupled between said first means and the drain electrode of said second transistor; a second impedance coupled between said first means and the gate electrode of said first transistor; a third insulated gate field effect transistor having a source, a drain and a gate electrode, the drain and source electrodes of whIch being respectively connected to the source electrode of said first insulated gate field effect transistor and said source of reference potential; an inverter means including a fourth and a fifth insulated gate field effect transistor connected in series between a second power source and said source of reference potential, the gate electrode of said fourth insulated gate field effect transistor being connected to the source electrode of said first insulated gate field effect transistor, and the gate electrodes of said third and fifth insulated gate field effect transistors being connected together to an input signal terminal; an output means for deriving an output from said inverter means connected to the source electrode of said fourth insulating gate field effect transistor; and further including a sixth insulated gate field effect transistor having a source, a drain and a gate electrode, the source electrode of which is connected to said second means, a second capacitor connected between the source electrode of said first transistor and the drain electrode of said sixth transistor, a third impedance connected between said first means and the drain electrode of said sixth transistor, and fourth means for coupling a second clock pulse, shifted in time relative to said first clock pulse, to the gate electrode of said sixth transistor.
Claim 3
Dependent Claim
57 words
A bootstrap circuit according to claim 1, wherein said second impedance comprises a seventh insulated gate field effect transistor, the source electrode of which is connected to the gate electrode of said first transistor, the drain electrode of which is connected to said first means, and the gate electrode of which is connected to said third means.
Claim 4
Dependent Claim
57 words
A bootstrap circuit according to claim 2, wherein said first impedance comprises a eighth insulated gate field effect transistor, the source electrode of which is connected to the drain electrode of said second transistor, the drain electrode of which is connected to said first means, and the gate electrode of which is connected to said fourth means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-09 | 1978-12-09 | 1979-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-09 | 1982-12-09 | 1983-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-09 | 1986-12-09 | 1987-06-10 | $7700.00 | Window Closed / Lapsed |