US5553231A
Expired / Lapsed
US
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Fault tolerant memory system
Assignee: Zitel Corp
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Filing: 1995-06-06
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Granted: 1996-09-03
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Expires: 2015-06-06
Abstract
Abstract A fault tolerant clock system is provided by utilizing redundant clocks which are maintained in synchronization, with voting circuit serving to select one of a plurality of matching clock signals for use. A resistor is coupled in series between the crystal and the oscillation circuit in order to establish a desired duty cycle of the clock signal. A series connected diode capacitor network is connected between a node of the oscillator circuit and a power supply in order to ensure initiation of oscillation.
Inventors
- 👤 Robert L. Papenberg
- 👤 Runchan D. Yang
- 👤 David H. Wotring
- 👤 Mohammad F. Rydhan
- 👤 Paul Voloshin
- 👤 Mohamed M. Talaat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:41
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/16; G06F11/1604; G06F11/10; G06F11/1008; G06F11/1048; G06F11/106; G06F11/1666; G06F11/167; G06F11/18; G06F11/183; G06F11/20; G06F11/2015; G11; G11C; G11C29/00; G11C29/70; G11C29/88; H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1675; G06F11/1679; G06F11/187; G06F11/22; G06F11/2205; G06F11/2215
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
176 words
A redundant clock circuit comprising: a plurality of synchronized clock generation circuits, each comprising: a plurality of input leads for receiving a plurality of clock signals from each of said plurality of synchronized clock generation circuits; a voter for selecting one of a plurality of matching ones of said plurality of clock signals; and an oscillation circuit comprising: a first inverter having an input lead serving as an input lead of said oscillation circuit, coupled to receive said selected one of said plurality of clock signals, and an output lead; a crystal having a first lead coupled to said output lead of said first inverter, and having an output lead; a second inverter having an input lead coupled to said output lead of said crystal, and having an output lead serving as an output lead of said oscillation circuit for providing a clock signal output; and a resistor coupled in series between said output lead of said crystal and said input lead of said second inverter to establish a desired duty cycle of said clock signal.
Claim 2
Dependent Claim
176 words
A redundant clock circuit comprising: a plurality of synchronized clock generation circuits, each comprising: a plurality of input leads for receiving a plurality of clock signals from each of said plurality of synchronized clock generation circuits; a voter for selecting one of a plurality of matching ones of said plurality of clock signals; and an oscillation circuit comprising: a first inverter having an input lead serving as an input lead of said oscillation circuit, coupled to receive said selected one of said plurality of clock signals, and an output lead; a crystal having a first lead coupled to said output lead of said first inverter, and having an output lead; a second inverter having an input lead coupled to said output lead of said crystal, and having an output lead serving as an output lead of said oscillation circuit for providing a clock signal output; and a resistor coupled in series between said output lead of said crystal and said input lead of said second inverter to establish a desired duty cycle of said clock signal.
Claim 3
Dependent Claim
45 words
A redundant clock circuit as in claim 1 wherein said oscillation circuit further comprises: a voltage divider having its center tap coupled to said input lead of said second inverter, thereby providing said second inverter with a known voltage level in the absence of oscillation.
Claim 4
Dependent Claim
34 words
A redundant clock circuit as in claim 1 wherein said oscillation circuit further comprises: a diode coupled in series with a capacitor between said input lead of said second inverter and a supply voltage.
Claim 5
Dependent Claim
36 words
A redundant clock circuit as in claim 1 wherein said voter selects one of said clock signals by deselecting clock signals which provide clock signals which are not substantially the same as others of said clocks.
Claim 6
Dependent Claim
166 words
A redundant clock circuit comprising: a plurality of synchronized clock generation circuits, each comprising: a plurality of input leads for receiving a plurality of clock signals from each of said plurality of synchronized clock generation circuits; a voter for selecting one of a plurality of matching ones of said plurality of clock signals; and an oscillation circuit comprising: a first inverter having an input lead serving as an input lead of said oscillation circuit, coupled to receive said selected one of said plurality of clock signals, and an output lead; a crystal having a first lead coupled to said output lead of said first inverter and having an output lead; a second inverter having an input lead coupled to said output lead of said crystal, and having an output lead serving as an output lead of said oscillation circuit for providing a clock signal output; and a diode coupled in series with a capacitor between said input lead of said second inverter and a supply voltage.
Claim 7
Dependent Claim
166 words
A redundant clock circuit comprising: a plurality of synchronized clock generation circuits, each comprising: a plurality of input leads for receiving a plurality of clock signals from each of said plurality of synchronized clock generation circuits; a voter for selecting one of a plurality of matching ones of said plurality of clock signals; and an oscillation circuit comprising: a first inverter having an input lead serving as an input lead of said oscillation circuit, coupled to receive said selected one of said plurality of clock signals, and an output lead; a crystal having a first lead coupled to said output lead of said first inverter and having an output lead; a second inverter having an input lead coupled to said output lead of said crystal, and having an output lead serving as an output lead of said oscillation circuit for providing a clock signal output; and a diode coupled in series with a capacitor between said input lead of said second inverter and a supply voltage.
Claim 8
Dependent Claim
45 words
A redundant clock circuit as in claim 5 wherein said oscillation circuit further comprises: a voltage divider having its center tap coupled to said input lead of said second inverter, thereby providing said second inverter with a known voltage level in the absence of oscillation.
Claim 9
Dependent Claim
36 words
A redundant clock circuit as in claim 5 wherein said voter selects one of said clock signals by deselecting clock signals which provide clock signals which are not substantially the same as others of said clocks.
Claim 10
Dependent Claim
44 words
A redundant clock circuit as in claim 5 wherein said oscillation circuit further comprises: a resistor coupled in series between said output lead of said crystal and said input lead of said second inverter to establish a desired duty cycle of said clock signal.
References Cited (Backward Citations)
US3218612A
Cited
US3921149A
Cited
US4016408A
Cited
US4021784A
Cited
US4183278A
Cited
US4307455A
Cited
US4277844A
Cited
US4363125A
Cited
US4461003A
Cited
US4453237A
Cited
US4547867A
Cited
US4375683A
Cited
US4384353A
Cited
US4523314A
Cited
US4644498A
Cited
US4827401A
Cited
US4757503A
Cited
US4683570A
Cited
US4839855A
Cited
US4805173A
Cited
US4920540A
Cited
US4817095A
Cited
US5005174A
Cited
US5027357A
Cited
US4965717B1
Cited
US5146589A
Cited
US4965717A
Cited
US5276823A
Cited
US4984241A
Cited
US4995041A
Cited
US4979191A
Cited
US5331645A
Cited
US5086429A
Cited
US5255270A
Cited
US5291498A
Cited
US5289478A
Cited
US5313624A
Cited
US5285456A
Cited
US5233615A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-03 | 2000-03-04 | 2000-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-03 | 2004-03-04 | 2004-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-03 | 2008-03-04 | 2008-09-03 | $7700.00 | Window Closed / Lapsed |