US5086429A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fault-tolerant digital computing system with reduced memory redundancy
Assignee: Honeywell Inc
•
Filing: 1990-04-10
•
Granted: 1992-02-04
•
Expires: 2010-04-10
Abstract
Abstract A highly reliable data processing system using the pair-spare architecture obviates the need for separate memory arrays for each processor. A single memory is shared between each pair of processors wherein a linear block code error detection scheme is implemented with each shared memory, wherein the effect of random memory faults is sufficiently detected such that the inherent fault tolerance of a pair-spare architecture is not compromised.
Inventors
- 👤 Scott L. Gray
- 👤 Steven R. Thompson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:34
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1641; G06F11/1645; G06F11/20; G06F11/202; G06F11/2038; G06F11/08; G06F11/10; G06F11/1008; G06F11/1044; G06F11/2043
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
323 words
A fail-operative, fail-pressure, fault-tolerant digital computer system comprising: (a) first and second pairs of substantially identical processor means with one pair being designated the active pair and the other designated the hot standby pair, each processor in each pair having an address bus and a data bus and each simultaneously clocked by a common mast clock and each programmed to simultaneously execute the same sequence of instructions in lock-step operation; (b) bus monitor means individually associated with each of said pair of processor means and operatively coupled to each address bus and said data bus for the processor means of each pair for detecting any discrepancies between the information being carried on said address buses and data buses of the individual processor means in said first and second pairs; (c) first and second shared memory means, each operatively coupled individually to said first and second pairs of processor means and each simultaneously accessed by said respective pairs of processor means such that said first and second shared memory means are identical; (d) first and second error detection means individually coupled intermediate said shared memory means and said address bus and said data bus of both processor means of each of said first pair and second pair of processor means for delivering a "fail" signal to said bus monitor means in the event a memory fault in said first and second shared memory means is detected by said error detection means; (e) system bus means coupled to said address bus and data bus for both the pair of processor means designated the active pair and said pair of processor means designated the hot standby pair; and (f) means coupling said bus monitor means to said system bus means for reversing the role of said active pair of processor means to a standby status and said pair of processor means designated the hot standby pair to an active status upon detection of said "fail" signal.
Claim 2
Dependent Claim
323 words
A fail-operative, fail-pressure, fault-tolerant digital computer system comprising: (a) first and second pairs of substantially identical processor means with one pair being designated the active pair and the other designated the hot standby pair, each processor in each pair having an address bus and a data bus and each simultaneously clocked by a common mast clock and each programmed to simultaneously execute the same sequence of instructions in lock-step operation; (b) bus monitor means individually associated with each of said pair of processor means and operatively coupled to each address bus and said data bus for the processor means of each pair for detecting any discrepancies between the information being carried on said address buses and data buses of the individual processor means in said first and second pairs; (c) first and second shared memory means, each operatively coupled individually to said first and second pairs of processor means and each simultaneously accessed by said respective pairs of processor means such that said first and second shared memory means are identical; (d) first and second error detection means individually coupled intermediate said shared memory means and said address bus and said data bus of both processor means of each of said first pair and second pair of processor means for delivering a "fail" signal to said bus monitor means in the event a memory fault in said first and second shared memory means is detected by said error detection means; (e) system bus means coupled to said address bus and data bus for both the pair of processor means designated the active pair and said pair of processor means designated the hot standby pair; and (f) means coupling said bus monitor means to said system bus means for reversing the role of said active pair of processor means to a standby status and said pair of processor means designated the hot standby pair to an active status upon detection of said "fail" signal.
Claim 3
Dependent Claim
114 words
The digital computing system as in claim 1 wherein said shared memory means for each of said first and second pairs of processor means further includes linear block code generating means for encoding data words from said processor means to be stored along with said data words in said shared memory means; and said first and second error detection mean includes syndrome generating means coupled to said data buses of said processors in said first and second pairs of processors for receiving said encoded data words being read out of said shared memory means for checking whether an error occurred in storing and reading out said encoded data words from said shared memory means.
References Cited (Backward Citations)
US4358823A
Cited
US4707781A
Cited
US4590551A
Cited
US4606066A
Cited
US4590554A
Cited
US4713811A
Cited
US4819232A
Cited
US4975838A
Cited
US5005174A
Cited
US4894828A
Cited
US4958768A
Cited
US4958270A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-03 | 1995-08-05 | 1996-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-03 | 1999-08-05 | 2000-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-03 | 2003-08-05 | 2004-02-04 | $7700.00 | Window Closed / Lapsed |