US4817095A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Byte write error code method and apparatus
Assignee: Hewlett Packard Development Co LP
•
Filing: 1987-05-15
•
Granted: 1989-03-28
•
Expires: 2007-05-15
Abstract
Abstract A method and apparatus for error detection is disclosed. A data word and its check bits are read from memory, and new check bits are generated form the data word read. A logical operation is performed between the new check bits and the check bits read from memory to generate a syndrome. The syndrome is decoded to detect the presence or absence of an uncorrectable error. If an uncorrectable error is detected, a logical operation is performed between the new check bits and a byte write error code to generate a third set of check bits, which are then written into memory along with the data word.
Inventors
- 👤 Donald W. Smelser
- 👤 James C. Stegeman
- 👤 Lawrence A. Chisvin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:52
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/1056; H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
110 words
A method for error detection comprising the steps of: (a) reading a data word from a memory; (b) reading from the memory a first set of check bits associated with the data word read; (c) generating a second set of check bits from the data word that has been read from the memory; (d) performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (e) decoding the syndrome in order to detect the presence or absence of an uncorrectable error, and upon the detection of an uncorrectable error, modifying the check bits to indicate such uncorrectable error.
Claim 2
Independent Claim
110 words
A method for error detection comprising the steps of: (a) reading a data word from a memory; (b) reading from the memory a first set of check bits associated with the data word read; (c) generating a second set of check bits from the data word that has been read from the memory; (d) performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (e) decoding the syndrome in order to detect the presence or absence of an uncorrectable error, and upon the detection of an uncorrectable error, modifying the check bits to indicate such uncorrectable error.
Claim 3
Dependent Claim
71 words
The method recited in claim 1, wherein the modification comprises: (i) performing a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits; (ii) writing the data word into the memory; and (iii) writing the third set of check bits into the memory so as to associate the third set of check bits with the data word.
Claim 4
Dependent Claim
52 words
The method recited in claim 2, wherein the first logical operation is an exclusive-OR operation between the first set of check bits and the second set of check bits and wherein the second logical operation is an exclusive-OR operation between the second set of check bits and a byte write error code.
Claim 5
Dependent Claim
39 words
The method recited in claim 2, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.
Claim 6
Dependent Claim
34 words
The method recited in claim 2, wherein the data word is 64 bits in length and wherein each set of the first, second, and third sets of check bits is 8 bits in length.
Claim 7
Dependent Claim
32 words
The method recited in claim 5 wherein the byte write error code is 01111111, wherein the left-most bit is the least significant bit and the right-most bit is the most significant bit.
Claim 8
Dependent Claim
29 words
The method recited in claim 6, further comprising the step of (f) indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.
Claim 9
Independent Claim
96 words
A method for error detection comprising the steps of: (a) reading a data word from a memory; (b) reading from the memory a first set of check bits associated with the data word read from the memory; (c) generating a second set of check bits from the data word that has been read from the memory; (d) performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; and (e) indicating a failed memory operation if the syndrome corresponds to a byte write error code.
Claim 10
Independent Claim
96 words
A method for error detection comprising the steps of: (a) reading a data word from a memory; (b) reading from the memory a first set of check bits associated with the data word read from the memory; (c) generating a second set of check bits from the data word that has been read from the memory; (d) performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; and (e) indicating a failed memory operation if the syndrome corresponds to a byte write error code.
Claim 11
Dependent Claim
29 words
The method recited in claim 8 further comprising the step of (f) indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.
Claim 12
Dependent Claim
43 words
The method recited in claim 9, wherein the byte write error code is surrounded by unused error codes such that the probability is increased that an uncorrectable error will be indicated if more than a single-bit error occurs after a failed memory operation.
Claim 13
Independent Claim
169 words
A method for error detection comprising the steps of: (a) reading a data word from a memory; (b) reading from the memory a first set of check bits associated with the data word read from the memory; (c) generating a second set of check bits from the data word that has been read from the memory; (d) performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (e) decoding the syndrome in order to detect the presence or absence of an uncorrectable error, and upon the detection of an uncorrectable error during a partial write operation, (i) performing a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits; (ii) writing the data word into the memory; (iii) writing the third set of check bits into the memory so as to associate the third set of check bits with the data word.
Claim 14
Independent Claim
169 words
A method for error detection comprising the steps of: (a) reading a data word from a memory; (b) reading from the memory a first set of check bits associated with the data word read from the memory; (c) generating a second set of check bits from the data word that has been read from the memory; (d) performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (e) decoding the syndrome in order to detect the presence or absence of an uncorrectable error, and upon the detection of an uncorrectable error during a partial write operation, (i) performing a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits; (ii) writing the data word into the memory; (iii) writing the third set of check bits into the memory so as to associate the third set of check bits with the data word.
Claim 15
Independent Claim
96 words
A method for error detection comprising the steps of: (a) reading a data word from a memory; (b) reading from the memory a first set of check bits associated with the data word read from the memory; (c) generating a second set of check bits from the data word that has been read from the memory; (d) performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (e) indicating a failed partial write operation if the syndrome corresponds to a byte write error code.
Claim 16
Independent Claim
96 words
A method for error detection comprising the steps of: (a) reading a data word from a memory; (b) reading from the memory a first set of check bits associated with the data word read from the memory; (c) generating a second set of check bits from the data word that has been read from the memory; (d) performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (e) indicating a failed partial write operation if the syndrome corresponds to a byte write error code.
Claim 17
Independent Claim
191 words
An apparatus for error detection comprising: (a) means for reading a data word from a memory; (b) means for reading from the memory a first set of check bits associated with the data word read from the memory; (c) means for generating a second set of check bits from the data word that has been read from the memory; (d) means for performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (e) means for decoding the syndrome in order to detect the presence or absence of an uncorrectable error; (f) means for performing, after the detection of an uncorrectable error, a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits; (g) means for writing, after the detection of an uncorrectable error, the data word into in the memory; (h) means for writing, after the detection of an uncorrectable error, the third set of check bits into the memory so as to associate the third set of check bits with the data word.
Claim 18
Independent Claim
191 words
An apparatus for error detection comprising: (a) means for reading a data word from a memory; (b) means for reading from the memory a first set of check bits associated with the data word read from the memory; (c) means for generating a second set of check bits from the data word that has been read from the memory; (d) means for performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (e) means for decoding the syndrome in order to detect the presence or absence of an uncorrectable error; (f) means for performing, after the detection of an uncorrectable error, a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits; (g) means for writing, after the detection of an uncorrectable error, the data word into in the memory; (h) means for writing, after the detection of an uncorrectable error, the third set of check bits into the memory so as to associate the third set of check bits with the data word.
Claim 19
Dependent Claim
53 words
The apparatus recited in claim 13, wherein the first logical operation is an exclusive-OR operation between the first set of check bits and the second set of check bits and wherein the second logical operation is an exclusive-OR logical operation between the second set of check bits and a byte write error code.
Claim 20
Dependent Claim
39 words
The apparatus recited in claim 13, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.
Claim 21
Dependent Claim
33 words
The apparatus recited in claim 13, wherein the data word is 64 bits in length and wherein each set of first, second, and third sets of check bits is 8 bits in length.
Claim 22
Dependent Claim
32 words
The apparatus recited in claim 16, wherein the byte write error code is 01111111, wherein the left-most bit is the least significant bit and the right-most bit is the most significant bit.
Claim 23
Independent Claim
103 words
An apparatus for error detection comprising: (a) means for reading a data word from a memory; (b) means for reading from the memory a first set of check bits associated with the data word read from the memory; (c) means for generating a second set of check bits from the data word that has been read from the memory; (d) means for performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; and (e) means for indicating a failed memory operation if the syndrome corresponds to a byte write error code.
Claim 24
Independent Claim
103 words
An apparatus for error detection comprising: (a) means for reading a data word from a memory; (b) means for reading from the memory a first set of check bits associated with the data word read from the memory; (c) means for generating a second set of check bits from the data word that has been read from the memory; (d) means for performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; and (e) means for indicating a failed memory operation if the syndrome corresponds to a byte write error code.
Claim 25
Dependent Claim
28 words
The apparatus recited in claim 14, further comprising: (f) means for indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.
Claim 26
Dependent Claim
39 words
The apparatus recited in claim 19, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.
Claim 27
Dependent Claim
209 words
A memory board for use in a data processing system and having error detection capability, comprising: (a) memory means for storing a plurality of data words; (b) means for reading a first one of the data words from the memory means; (c) means for reading form the memory means a first set of check bits associated with the first data word; (d) means for generating a second set of check bits from the first data word; (e) means for performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (f) means for decoding the syndrome in order to detect the presence of an uncorrectable error; (g) means for performing, after the detection of an uncorrectable error, a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits; (h) means for writing, after the detection of an uncorrectable error, the first data word into the memory means; (i) means for writing, after the detection of an uncorrectable error, the third set of check bits into the memory means so as to associate the third set of check bits with the first data word.
Claim 28
Dependent Claim
209 words
A memory board for use in a data processing system and having error detection capability, comprising: (a) memory means for storing a plurality of data words; (b) means for reading a first one of the data words from the memory means; (c) means for reading form the memory means a first set of check bits associated with the first data word; (d) means for generating a second set of check bits from the first data word; (e) means for performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (f) means for decoding the syndrome in order to detect the presence of an uncorrectable error; (g) means for performing, after the detection of an uncorrectable error, a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits; (h) means for writing, after the detection of an uncorrectable error, the first data word into the memory means; (i) means for writing, after the detection of an uncorrectable error, the third set of check bits into the memory means so as to associate the third set of check bits with the first data word.
Claim 29
Dependent Claim
54 words
The memory board recited in claim 21, wherein the first logical operation is an exclusive-OR operation between the first set of check bits and the second set of check bits and wherein the second logical operation is an exclusiveOR logical operation between the second set of check bits and a byte write error code.
Claim 30
Dependent Claim
40 words
The memory board recited in claim 21, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier undetected uncorrectable error.
Claim 31
Dependent Claim
34 words
The memory board recited in claim 21, wherein the data word is 64 bits in length and wherein each set of first, second, and third sets of check bits is 8 bits in length.
Claim 32
Dependent Claim
33 words
The memory board recited in claim 24, wherein the byte write error code is 01111111, wherein the left-most bit is the least significant bit and the right-most bit is the most significant bit.
Claim 33
Dependent Claim
119 words
A memory board for use in a data processing system and having error detection capability, comprising: (a) memory means for storing a plurality of data words; (b) means for reading a first one of the data words from the memory means; (c) means for reading from the memory means a first set of check bits associated with the first data word; (d) means for generating a second set of check bits from the first data word; (e) means for performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (f) means for indicating a failed memory operation if the syndrome corresponds to a byte write error. code.
Claim 34
Dependent Claim
119 words
A memory board for use in a data processing system and having error detection capability, comprising: (a) memory means for storing a plurality of data words; (b) means for reading a first one of the data words from the memory means; (c) means for reading from the memory means a first set of check bits associated with the first data word; (d) means for generating a second set of check bits from the first data word; (e) means for performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (f) means for indicating a failed memory operation if the syndrome corresponds to a byte write error. code.
Claim 35
Dependent Claim
29 words
The memory board recited in claim 26, further comprising: (f) means for indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.
Claim 36
Dependent Claim
40 words
The memory board recited in claim 27, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.
Claim 37
Dependent Claim
234 words
An error detecting memory system, for use in a data processing system having a data bus, (a) means for receiving data words from the data bus; (b) means for generating check bits for each of the received data words; (c) memory means for storing the received data words and the generated check bits; (d) means for reading a first one of the data words from the memory means; (e) means for reading from the memory means a first set of check bits associated with the first data word; (f) means for generating a second set of check bits from the first data word; (g) means for performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (h) means for decoding the syndrome to detect the presence of an uncorrectable error; (i) means for performing, after the detection of an uncorrectable error, a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits; (j) means for writing, after the detection of an uncorrectable error, the first data word into the memory means; (k) means for writing, after the detection of an uncorrectable error, the third set of check bits into the memory means so as to associated the third set of check bits with the first data word.
Claim 38
Dependent Claim
234 words
An error detecting memory system, for use in a data processing system having a data bus, (a) means for receiving data words from the data bus; (b) means for generating check bits for each of the received data words; (c) memory means for storing the received data words and the generated check bits; (d) means for reading a first one of the data words from the memory means; (e) means for reading from the memory means a first set of check bits associated with the first data word; (f) means for generating a second set of check bits from the first data word; (g) means for performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (h) means for decoding the syndrome to detect the presence of an uncorrectable error; (i) means for performing, after the detection of an uncorrectable error, a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits; (j) means for writing, after the detection of an uncorrectable error, the first data word into the memory means; (k) means for writing, after the detection of an uncorrectable error, the third set of check bits into the memory means so as to associated the third set of check bits with the first data word.
Claim 39
Dependent Claim
29 words
The memory system recited in claim 29, further comprising: (f) means for indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.
Claim 40
Dependent Claim
40 words
The memory system recited in claim 30, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.
Claim 41
Dependent Claim
54 words
The memory system recited in claim 29, wherein the first logical operation is an exclusive-OR operation between the first set of check bits and the second set of check bits and wherein the second logical operation is an exclusive-OR logical operation between the second set of check bits and a byte write error code.
Claim 42
Dependent Claim
40 words
The memory system recited in claim 29, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.
Claim 43
Dependent Claim
34 words
The memory system recited in claim 29, wherein the data word is 64 bits in length and wherein each set of first, second, and third sets of check bits is 8 bits in length.
Claim 44
Dependent Claim
33 words
The memory system recited in claim 34 wherein the byte write error code is 01111111, wherein the left-most bit is the least significant bit and the right-most bit is the most significant bit.
Claim 45
Dependent Claim
147 words
An error detecting memory system, for use in a data processing system having a data bus, comprising: (a) means for receiving data words from the data bus; (b) means for generating check bits for each of the received data words; (c) memory means for storing the received data words and the generated check bits; (d) means for reading a first one of the data words from the memory means; (e) means for reading from the memory means a first set of check bits associated with the first data word; (f) means for generating a second set of check bits from the first data word; (g) means for performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (h) means for indicating a failed memory operation if the syndrome corresponds to a byte write error code.
Claim 46
Dependent Claim
147 words
An error detecting memory system, for use in a data processing system having a data bus, comprising: (a) means for receiving data words from the data bus; (b) means for generating check bits for each of the received data words; (c) memory means for storing the received data words and the generated check bits; (d) means for reading a first one of the data words from the memory means; (e) means for reading from the memory means a first set of check bits associated with the first data word; (f) means for generating a second set of check bits from the first data word; (g) means for performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; (h) means for indicating a failed memory operation if the syndrome corresponds to a byte write error code.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-27 | 1992-09-26 | 1993-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-27 | 1996-09-26 | 1997-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-27 | 2000-09-26 | 2001-03-28 | $7700.00 | Window Closed / Lapsed |