US5313624A
Expired / Lapsed
US
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DRAM multiplexer
Assignee: Next Computer Inc
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Filing: 1991-05-14
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Granted: 1994-05-17
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Expires: 2011-05-14
Abstract
Abstract The present invention provides a system for supporting one or more memory requestors (CPU's and I/O DMA) accessing a plurality of DRAM memory banks. The present invention is a multiplexer that functions as a 16-bit slice of the interface between the CPU and a 64-bit slice of DRAM memory array. The invention includes an error correction (ECC) module, a 64-bit DRAM I/O channel, an 8-bit ECC "syndrome" I/O channel and an 8-bit slice of a DMA bus I/O channel. In a write operation, the CPU transmits data through the I/O channel to write the data to the DRAM. Each word is routed by the four-way multiplexer to one of the four memory registers. When the four registers have been filled with data words, the words are assembled into a multiple word burst and sent to the DRAM bank. The data is also passed through an error correction module. For a read operation, DRAM data is latched into the CPU register and transported to the CPU while the DRAM is potentially being accessed for another memory read.
Inventors
- 👤 Guy Harriman
- 👤 Mark Ross
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:09
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1044; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1678; G06F13/20; G06F13/28; G06F13/287
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
68 words
A memory multiplexor for providing an interface between a processing means and a plurality of memory banks comprising: a first bus for communicating with said processing means; multiplexing means coupled to said first bus; a plurality of registers coupled to said multiplexing means; error correction means coupled to said plurality of registers; a second bus coupled to said error correction means and to said plurality of memory banks.
Claim 2
Dependent Claim
68 words
A memory multiplexor for providing an interface between a processing means and a plurality of memory banks comprising: a first bus for communicating with said processing means; multiplexing means coupled to said first bus; a plurality of registers coupled to said multiplexing means; error correction means coupled to said plurality of registers; a second bus coupled to said error correction means and to said plurality of memory banks.
Claim 3
Dependent Claim
14 words
The multiplexor of claim 1 wherein said first bus comprises a sixteen bit bus.
Claim 4
Dependent Claim
14 words
The multiplexor of claim 2 wherein said second bus comprises a 64 bit bus.
Claim 5
Dependent Claim
15 words
The multiplexor of claim 1 wherein said multiplexing means comprises a four to one multiplexor.
Claim 6
Dependent Claim
23 words
The multiplexor of claim 1 wherein said plurality of registers are such that a memory access can be overlapped with a data transfer.
Claim 7
Dependent Claim
38 words
The multiplexor of claim 1 wherein said error correcting means generates an error correction syndrome when data is written to said plurality of memory banks and said syndrome and said data are both provided to said memory banks.
Claim 8
Dependent Claim
24 words
The multiplexor of claim 1 wherein said plurality of registers includes a first plurality of read registers and a second plurality of write registers.
Claim 9
Independent Claim
88 words
A method of communicating between a central processing unit (cpu) and a storage means comprised of a plurality of memory banks, said method comprising the steps of: providing data words from said cpu to a multiplexor interface means coupled to said cpu and said memory banks; storing a first number of said data words in registers in said interface means; outputting a data word burst to said memory banks, said data word burst comprising said first number of data words; storing said data word burst in memory banks.
Claim 10
Independent Claim
88 words
A method of communicating between a central processing unit (cpu) and a storage means comprised of a plurality of memory banks, said method comprising the steps of: providing data words from said cpu to a multiplexor interface means coupled to said cpu and said memory banks; storing a first number of said data words in registers in said interface means; outputting a data word burst to said memory banks, said data word burst comprising said first number of data words; storing said data word burst in memory banks.
Claim 11
Dependent Claim
42 words
The method of claim 8 further including the steps of: generating an error correction syndrome in said interface means from said first number of data words; transmitting said syndrome from said interface means to said memory banks with said data word burst.
Claim 12
Dependent Claim
20 words
The method of claim 9 wherein said first number of data words comprises four data words from said first bus.
Claim 13
Dependent Claim
16 words
The method of claim 10 wherein said syndrome is generated by an ECC error correction module.
Claim 14
Independent Claim
85 words
A method of communicating between a central processing unit (cpu) and a storage means comprising a plurality of memory banks, said method comprising the steps of: providing a data word burst comprising a first number of data words from said memory banks to a multiplexor interface means coupled to said cpu and to said memory banks; storing said first number of data words in a plurality of registers in said interface means; transmitting said first number of data words from said registers to said cpu.
Claim 15
Independent Claim
85 words
A method of communicating between a central processing unit (cpu) and a storage means comprising a plurality of memory banks, said method comprising the steps of: providing a data word burst comprising a first number of data words from said memory banks to a multiplexor interface means coupled to said cpu and to said memory banks; storing said first number of data words in a plurality of registers in said interface means; transmitting said first number of data words from said registers to said cpu.
Claim 16
Dependent Claim
55 words
The method of claim 12 further including the steps of: transmitting an error correction syndrome to said registers with said data word burst; comparing said transmitted error correction syndrome to a previously stored error correction syndrome; determining if an error exists in said data word burst; correcting said data word burst when an error exists.
Claim 17
Dependent Claim
16 words
The method of claim 13 wherein said first number of data words comprises four data words.
Claim 18
Dependent Claim
34 words
The method of claim 14 wherein said step of comparing said transmitted error correction syndrome to said previously stored error correction syndrome is performed in an error correction module of said multiplexor interface means.
Claim 19
Dependent Claim
41 words
The method of claim 12 further including the step transmitting another data word burst from said memory banks to said interface means while said step of transmitting said first number of data words from said registers to said cpu is performed.
Claim 20
Independent Claim
91 words
A method of communicating between a direct memory access (DMA) device and a storage means comprised of a plurality of memory banks, said method comprising the steps of: providing data words from said DMA device to a multiplexor interface means coupled to said DMA device and said memory banks; storing a first number of said data words in registers in said interface means; outputting a data word burst to said memory banks, said data word burst comprising said first number of data words; storing said data word burst in memory banks.
Claim 21
Independent Claim
91 words
A method of communicating between a direct memory access (DMA) device and a storage means comprised of a plurality of memory banks, said method comprising the steps of: providing data words from said DMA device to a multiplexor interface means coupled to said DMA device and said memory banks; storing a first number of said data words in registers in said interface means; outputting a data word burst to said memory banks, said data word burst comprising said first number of data words; storing said data word burst in memory banks.
Claim 22
Dependent Claim
42 words
The method of claim 17 further including the steps of: generating an error correction syndrome in said interface means from said first number of data words; transmitting said syndrome from said interface means to said memory banks with said data word burst.
Claim 23
Independent Claim
88 words
A method of communicating between a direct memory access (DMA) device and a storage means comprising a plurality of memory banks, said method comprising the steps of: providing a data word burst comprising a first number of data words from said memory banks to a multiplexor interface means coupled to said DMA device and to said memory banks; storing said first number of data words in a plurality of registers in said interface means; transmitting said first number of data words from said registers to said DMA device.
Claim 24
Independent Claim
88 words
A method of communicating between a direct memory access (DMA) device and a storage means comprising a plurality of memory banks, said method comprising the steps of: providing a data word burst comprising a first number of data words from said memory banks to a multiplexor interface means coupled to said DMA device and to said memory banks; storing said first number of data words in a plurality of registers in said interface means; transmitting said first number of data words from said registers to said DMA device.
Claim 25
Dependent Claim
55 words
The method of claim 19 further including the steps of: transmitting an error correction syndrome to said registers with said data word burst; comparing said transmitting error correction syndrome to a previously stored error correction syndrome; determining if an error exists in said data word burst; correcting said data word burst when an error exists.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-16 | 1997-11-15 | 1998-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-16 | 2001-11-15 | 2002-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-16 | 2005-11-15 | 2006-05-17 | $7700.00 | Window Closed / Lapsed |