US4688166A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Direct memory access controller supporting multiple input/output controllers and memory units
Assignee: Motorola Solutions Inc
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Filing: 1984-08-03
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Granted: 1987-08-18
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Expires: 2004-08-03
Abstract
Abstract A direct memory access controller (8, FIG. 1) is provided which can service a number of input/output controllers (24, 26) concurrently on a time-division multiplexed basis. The direct memory access controller 8 (DMAC) is capable of interconnecting more than one input/output device (64, 66, 69, 74, 76) with more than one system memory (2, 20). The DMAC 8 can also transfer data from one system memory (2) to a second system memory (20), or within one system memory.
Inventors
- 👤 Glenn H. Schneider
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:37
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
159 words
In a data processing system comprising a central processing unit, at least two memory units each storing instructions and data for processing by said central processing unit, and at least two input/output controllers each requiring access to each of said memory units, the improvement wherein said data processing system further comprises a direct access memory controller coupled between said input/output controllers and said memory units, said memeory controller enabling either input/output controller to access either of said memory units directly without generating a processor interrupt operation in said processing unit and without interrupting the operation of the other memory unit, and wherein said memory controller comprises multiplexer means coupled to said input/output controllers, said multiplexer means comprising means for coupling a first one of said input/output controllers to a first one of said memory units, and means for coupling a second one of said input/output controllers to a second one of said memory units in a time-division multiplexed manner.
Claim 2
Dependent Claim
159 words
In a data processing system comprising a central processing unit, at least two memory units each storing instructions and data for processing by said central processing unit, and at least two input/output controllers each requiring access to each of said memory units, the improvement wherein said data processing system further comprises a direct access memory controller coupled between said input/output controllers and said memory units, said memeory controller enabling either input/output controller to access either of said memory units directly without generating a processor interrupt operation in said processing unit and without interrupting the operation of the other memory unit, and wherein said memory controller comprises multiplexer means coupled to said input/output controllers, said multiplexer means comprising means for coupling a first one of said input/output controllers to a first one of said memory units, and means for coupling a second one of said input/output controllers to a second one of said memory units in a time-division multiplexed manner.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-17 | 1991-02-16 | 1991-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-17 | 1995-02-16 | 1995-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-17 | 1999-02-16 | 1999-08-18 | $7700.00 | Window Closed / Lapsed |