US4920540A
Expired / Lapsed
US
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Fault-tolerant digital timing apparatus and method
Assignee: Ascend Communications Inc
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Filing: 1987-02-25
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Granted: 1990-04-24
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Expires: 2007-02-25
Abstract
Abstract Computer timing apparatus enables two redundant strobe or clock elements (11, 12) to produce a single stream of timing pulses (CLK*), without interruption, when both elements are operating normally, and when one element fails. The apparatus incorporates a multi-stable stage (21, 22, 23, 24) and an output logic stage (25, 26, 27). The multi-stable stage detects state transitions in the input signals (CLK1, CLK2) of each clock element and generates a corresponding clock-tracking signal (TRACK1, TRACK2) which can disable the output of the corresponding clock from propagating through the output logic. The output logic stage logically combines each clock signal (CLK1 or CLK2) with its corresponding clock-tracking signal (TRACK1 or TRACK2), and logically combines the resultant signal to produce a single stream of output signals (CLK*) responsive to a next transition produced by either of the two strobe or clock elements.
Inventors
- 👤 Kurt F. Baty
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:05
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1604; G06F11/14; G06F11/1402; G06F11/1608; G06F11/1625; G06F11/20; G06F11/2002; G06F11/2005; G06F11/2007; G06F11/2017; G06F11/22; G06F1/00; G06F1/04; G06F11/1629; G06F11/1666
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
223 words
A digital logic circuit for generating a reliable serial stream of clock output pulses from first and second digital input clocks, said circuit comprising: A. first and second input means for receiving clock input pulses produced from said first and second clocks respectively, B. first bi-stable logic means associated with said first input means, for storing a first digital value received at said first input means and selectively transmitting, responsive to pulses received at said second input means, said first digital value or a complementary digital value of said first digital value, C. second bi-stable logic means associated with said second input means, for storing a second digital value received at said second input means and selectively transmitting, responsive to pulses received at said first input means, said second digital value or a complementary digital value of said second digital value, D. output logic means, connected with said first and second input means and with said first and second bi-stable logic means, for (i) comparing pulses from said first and second input means, and from said first and second bi-stable logic means, and (ii) producing a clock output pulse in response to a next clock input pulse received at either of said input means, so that an uninterrupted clock pulse output is produced notwithstanding failure of any single one of said input clocks.
Claim 2
Dependent Claim
223 words
A digital logic circuit for generating a reliable serial stream of clock output pulses from first and second digital input clocks, said circuit comprising: A. first and second input means for receiving clock input pulses produced from said first and second clocks respectively, B. first bi-stable logic means associated with said first input means, for storing a first digital value received at said first input means and selectively transmitting, responsive to pulses received at said second input means, said first digital value or a complementary digital value of said first digital value, C. second bi-stable logic means associated with said second input means, for storing a second digital value received at said second input means and selectively transmitting, responsive to pulses received at said first input means, said second digital value or a complementary digital value of said second digital value, D. output logic means, connected with said first and second input means and with said first and second bi-stable logic means, for (i) comparing pulses from said first and second input means, and from said first and second bi-stable logic means, and (ii) producing a clock output pulse in response to a next clock input pulse received at either of said input means, so that an uninterrupted clock pulse output is produced notwithstanding failure of any single one of said input clocks.
Claim 3
Dependent Claim
138 words
Computer timing apparatus for producing a single stream of timing pulses continually when at least any one of first and second input sequences of timing signals are present, said apparatus comprising A. multi-stable binary logic means for receiving said first and second input sequences of timing signals and for producing, in response thereto, first and second sequences of clock-tracking signals, each sequence of clock-tracking signals being responsive to occurrence of a transition in at least one input sequence of timing signals, and B. output logic means for logically combining each input sequence of timing signals with its corresponding clock-tracking signal to generate a corresponding resultant signal, and for logically combining the resultant signals to produce a single stream of output signals responsive to a next transition in any of said first and second input sequences of timing signals.
Claim 4
Dependent Claim
138 words
Computer timing apparatus for producing a single stream of timing pulses continually when at least any one of first and second input sequences of timing signals are present, said apparatus comprising A. multi-stable binary logic means for receiving said first and second input sequences of timing signals and for producing, in response thereto, first and second sequences of clock-tracking signals, each sequence of clock-tracking signals being responsive to occurrence of a transition in at least one input sequence of timing signals, and B. output logic means for logically combining each input sequence of timing signals with its corresponding clock-tracking signal to generate a corresponding resultant signal, and for logically combining the resultant signals to produce a single stream of output signals responsive to a next transition in any of said first and second input sequences of timing signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-23 | 1993-10-23 | 1994-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-23 | 1997-10-23 | 1998-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-23 | 2001-10-23 | 2002-04-24 | $7700.00 | Window Closed / Lapsed |