Fault tolerant clock apparatus utilizing a controlled minority of clock elements

Claim 1

A fault tolerant clock apparatus for providing a digital clock signal despite a number r of failures of individual clock elements thereof, said apparatus comprising: a plurality of n individual clock elements connected to each other to receive output clock signals from all of said plurality of clock elements, each of said clock elements including quorum logic means for forming control signals responsive to transitions between digital logic levels in the output signals of a controlling minority of a number x of said individual clock elements, output means comprising bistable digital logic means electrically connected to said quorum logic means for forming the digital clock signal in response to the control signals from said quorum logic means wherein the clock signal is formed despite failure of individual clock elements in the clock apparatus, said quorum logic means forming a first of said control signals for setting the output bistable logic means to a first logic level in response to transitions in logic level of the controlling minority x of individual clock elements and said quorum logic means forming a second of said control signals for resetting the output bistable logic means to the second logic level in response to transitions in logic levels of an integral number y of clock elements wherein r, n, and x are positive integers, x is equal to or greater than r+1, n is equal to or greater than 3r+1, and y is equal to or less than n-r.