Majority logic system

Claim 2

A majority logic system comprising a plurality of channels of shift registers, means for triggering said shift registers to generate signals in synchronism, and means for comparing signals from the shift register of one of said channels with signals from the shift registers of two of the other said channels to effect synchronism of all of the compared signals.

Claim 3

A majority logic system comprising a plurality of redundant multiphase signal generating means, each comprising means for generating a bi-state signal having components of mutually different phase, means for transmitting each component of said signal to at least two of the other generating means, means for comparing the states of each component of signals received from other signal generating means with the states of each corresponding component of its own bi-state signal, and means for changing the state of any one component of its own bi-state signal when it does not agree with the state of the corresponding components of two other signals.

Claim 4

A majority logic system comprising a plurality of redundant multiphase signal generating means, each comprising means for generating a bi-state signal having components of mutually different phase, means for transmitting each component of said signal to at least two of the other generating means, means for comparing the states of each component of signals received from other signal generating means with the states of each corresponding component of its own bi-state signal, and means for changing the state of any one component of its own bi-state signal when it does not agree with the state of the corresponding components of two other signals.

Claim 5

A majority logic system comprising a plurality of redundant and nominally synchronous bi-state signal handling circuits, and logic means within each individual circuit responsive to the outputs of at least two of the other circuit outputs for changing the state of the output of such individual circuit only when it differs from the state of the output of more than one of the other circuits.

Claim 6

A majority logic system comprising a plurality of redundant and nominally synchronous bi-state signal handling circuits, and logic means within each individual circuit responsive to the outputs of at least two of the other circuit outputs for changing the state of the output of such individual circuit only when it differs from the state of the output of more than one of the other circuits.

Claim 7

The system of claim 2 including a source of clock signals, each circuit comprising a first flip-flop connected to be set and reset in synchronism by said clock signals, said logic means for each individual circuit comprising a coincidence gate responsive to a signal of one state from the flip-flop of such individual circuit and to signals of opposite states from the flip-flops of at least two other circuits, and means for momentarily disabling said coincidence gate for a time during and immediately following each of said clock signals.

Claim 8

The system of claim 4 including a source of drive pulses, each circuit comprising a second and third flip-flop, means for connecting said flip-flops to change state upon each fourth clock signal to provide a three phase output, second and third logic means for said second and third flip-flops, each substantially similar to said first mentioned logic means and each connected with second flip-flops and third flip-flops of a plurality of said circuits in the same manner as said first mentioned logic means is connected with said first flip-flops, a plurality of drive pulse coincidence gates, each having a first input from an individual one of the flip-flops of one of said signal handling circuits, and each having a second input from said source of drive pulses whereby a plurality of redundant sets of multiphase modulated drive pulses is provided from said drive pulse gates.

Claim 9

A multiphase signal handling circuit comprising means for providing clock signals, means for providing a drive signal comprising a train of drive pulses, and a plurality of modulating channels responsive to said clock and drive signals for providing a number of redundant sets of said drive signals modulated with mutually different phases, each said channel comprising means for generating a plurality of modulator gate signals of respectively different phases, means for comparing modulator gate signals of like phase from at least three of said channels and mutually synchronizing compared signals, and means for modulating the drive signal by each said gate signal.

Claim 10

A multiphase signal handling circuit comprising means for providing clock signals, means for providing a drive signal comprising a train of drive pulses, and a plurality of modulating channels responsive to said clock and drive signals for providing a number of redundant sets of said drive signals modulated with mutually different phases, each said channel comprising means for generating a plurality of modulator gate signals of respectively different phases, means for comparing modulator gate signals of like phase from at least three of said channels and mutually synchronizing compared signals, and means for modulating the drive signal by each said gate signal.

Claim 11

A redundant multiphase signal handling system comprising means for providing a train of clock pulses at a repetition rate of N times the repetition rate of said multiphase signal, where N is the number of phases of said mutliphase signal, and a plurality of channels of phase generators each comprising means responsive to said clock pulses for generating N phase control pulses each being phase displaced from a phase control pulse of earlier phase by the interval between clock pulses, logic means for each individual phase of phase control pulses for comparing such individual pulse with a corresponding pulse of at least two other channels, and means responsive to said logic means for changing such individual pulse when disagreement with said two other channel compared pulses occurs.

Claim 12

A redundant multiphase signal handling system comprising means for providing a train of clock pulses at a repetition rate of N times the repetition rate of said multiphase signal, where N is the number of phases of said mutliphase signal, and a plurality of channels of phase generators each comprising means responsive to said clock pulses for generating N phase control pulses each being phase displaced from a phase control pulse of earlier phase by the interval between clock pulses, logic means for each individual phase of phase control pulses for comparing such individual pulse with a corresponding pulse of at least two other channels, and means responsive to said logic means for changing such individual pulse when disagreement with said two other channel compared pulses occurs.

Claim 13

The system of claim 7 including means for providing a train of drive pulses, each said channel including a plurality of modulators, each modulator having a first input from said drive pulses, and a second input from a different phase of said phase control pulses.

Claim 14

The system of claim 8 wherein each channel includes means for monitoring the output of said logic means, and means responsive to said monitoring means for indicating occurrence of said disagreement at a plurality of successive clock pulses.

Claim 15

The system of claim 9 wherein said means for indicating occurrence of disagreement comprises a capacitor for storing signals indicating disagreement, and means responsive to a predetermined charge on said capacitor for generating an alarm signal.

Claim 16

The system of claim 7 wherein said phase control pulse generating means of each channel comprises a shift register having a triggering input from said clock pulses and having a plurality of stages, each stage having outputs providing two of said phase control pulses of mutually opposite phase, said logic means for each individual channel comprising a first coincidence gate for each of said shift register stages having inputs from one of said stage outputs and from corresponding outputs of corresponding stages of said two other channels, and a second coincidence gate for each of said shift register stages having inputs from the other of said stage outputs and from corresponding outputs of corresponding stages of said two other channels, said means for changing an individual pulse comprising means responsive to each of the coincidence gates for changing the state of the corresponding shift register stage.

Claim 17

The system of claim 11 including means for momentarily disabling each said coincIdence gate during and immediately after each clock pulse.

Claim 18

The system of claim 11 wherein each channel includes an OR gate responsive to each said coincidence gate for providing an out of synchronization signal, first and second input diodes having first and second input terminals and having output terminals connected in common, said second input terminal being connected to said OR gate to receive said out of synchronization signal, a switching device having an output terminal and having an input connected to said commonly connected diode output terminal, and a parallel capacitor-resistor circuit connected to the input terminal of said first diode, whereby a signal of predetermined character at the input terminal of the second diode will charge the capacitor sufficiently to provide an input to the first diode.

Claim 19

A multichannel, multiphase signal circuit comprising a source of clock pulses, a source of drive pulses, and a plurality of channels of phase generators, each channel comprising first, second, and third flip-flops connected to form a shift register that shifts in a predetermined sequence in response to an input from said clock pulse source, each flip-flop having a direct set and reset input, and a first and second output, a plurality of modulator gates, each having a first input from said source of drive pulses, and a second input from a respective one of said first and second outputs of said first, second, and third flip-flops, a plurality of output gates responsive to a first output of each flip-flop for transmitting said first output of such flip-flop to each of the other channels, a plurality of output gates connected to the second output of each flip-flop for transmitting the second output of such flip-flop to each of the other channels, a coincidence gate for each direct input of each flip-flop, each coincidence gate having an output connected to one of the direct inputs of the flip-flop, a first input from the first output of the flip-flop, and second and third inputs from corresponding outputs of corresponding flip-flops of each of two other channels.

Claim 20

A multichannel, multiphase signal circuit comprising a source of clock pulses, a source of drive pulses, and a plurality of channels of phase generators, each channel comprising first, second, and third flip-flops connected to form a shift register that shifts in a predetermined sequence in response to an input from said clock pulse source, each flip-flop having a direct set and reset input, and a first and second output, a plurality of modulator gates, each having a first input from said source of drive pulses, and a second input from a respective one of said first and second outputs of said first, second, and third flip-flops, a plurality of output gates responsive to a first output of each flip-flop for transmitting said first output of such flip-flop to each of the other channels, a plurality of output gates connected to the second output of each flip-flop for transmitting the second output of such flip-flop to each of the other channels, a coincidence gate for each direct input of each flip-flop, each coincidence gate having an output connected to one of the direct inputs of the flip-flop, a first input from the first output of the flip-flop, and second and third inputs from corresponding outputs of corresponding flip-flops of each of two other channels.

Claim 21

The circuit of claim 14 including means for disabling each of said coincidence gates of each channel for an interval that begins with each clock pulse and that terminates before the next one of said drive pulses.

Claim 22

The circuit of claim 14 wherein said drive pulses have a repetition rate that is a multiple of the repetion rate of said clock pulses, and wherein each drive pulse that occurs in coincidence with a clock pulse is suppressed.

Claim 23

The system of claim 14 including an OR gate having an input from each of the outputs of each of the coincidence gates, and a timing circuit having an input from the output of the OR gate for providing a synchronization error output signal upon receipt of a predetermined minimum number of pulses from the OR gate or upon receipt of any continuous output signal from the OR gate.

Claim 24

The system of claim 17 including an integrating circuit connected between the output of each of said coincidence gates and said OR gate.

Claim 25

A redundant majority logic system comprising a plurality of redundant channels of signal generating circuits, means for triggering each of said circuits to generate signals in mutual synchronism, means for comparing signals from the circuit of one of said channels with signals from the circuits of two of the other said channels, and means responsive to said comparing means for enforcing synchronism of the signal of said one channel with the signals of said other two channels when the signal of said one channel is out of synchronism with the signals from both of said other two channels.

Claim 26

A redundant majority logic system comprising a plurality of redundant channels of signal generating circuits, means for triggering each of said circuits to generate signals in mutual synchronism, means for comparing signals from the circuit of one of said channels with signals from the circuits of two of the other said channels, and means responsive to said comparing means for enforcing synchronism of the signal of said one channel with the signals of said other two channels when the signal of said one channel is out of synchronism with the signals from both of said other two channels.

Claim 27

A majority logic system comprising a plurality of channels of shift registers, means for triggering said shift registers to generate signals in synchronism, anD means for comparing signals from the shift registers of one of said channels with signals from the shift registers of two of the other of said channels to effect synchronism of all of the compared signals, said last-mentioned means comprising means for changing the signal from said one channel only when it is out of synchronism with signals from both of said other channels.

Claim 28

A majority logic system comprising a plurality of channels of shift registers, means for triggering said shift registers to generate signals in synchronism, anD means for comparing signals from the shift registers of one of said channels with signals from the shift registers of two of the other of said channels to effect synchronism of all of the compared signals, said last-mentioned means comprising means for changing the signal from said one channel only when it is out of synchronism with signals from both of said other channels.

Claim 29

A mutliphase signal handling circuit comprising means for providing clock signals, means for providing a drive signal comprising a train of drive pulses, and a pluraltiy of modulating channels responsive to said clock and drive signals for providing a number of redundant sets of said drive signals modulated with mutually different phases, each said channel comprising means for generating a plurality of modulator gate signals of respectively different phases, means for comparing modulator gate signals of like phase from at least three of said channels and mutually synchronizing compared signals, and means for modulating the drive signal by each said gate signal, each said comparing means comprising comparator means within each individual channel for generating a disagreement signal only when the gate signal of such individual channel fails to agree with the gate signals of like phase from at least two other channels, and means responsive to said disagreement signal for changing the gate signal of such individual channel to agree with said signals of like phase from said other channels.

Claim 30

A mutliphase signal handling circuit comprising means for providing clock signals, means for providing a drive signal comprising a train of drive pulses, and a pluraltiy of modulating channels responsive to said clock and drive signals for providing a number of redundant sets of said drive signals modulated with mutually different phases, each said channel comprising means for generating a plurality of modulator gate signals of respectively different phases, means for comparing modulator gate signals of like phase from at least three of said channels and mutually synchronizing compared signals, and means for modulating the drive signal by each said gate signal, each said comparing means comprising comparator means within each individual channel for generating a disagreement signal only when the gate signal of such individual channel fails to agree with the gate signals of like phase from at least two other channels, and means responsive to said disagreement signal for changing the gate signal of such individual channel to agree with said signals of like phase from said other channels.