Method and means for internal error check in a digital memory

Claim 1

An error detection apparatus responsive to an ED signal, an ED' signal, data and an external error check code received from an external source, with means for coupling said apparatus to a memory having a storing cycle and a reading cycle and an output buffer, comprising: means, responsive to said ED signal, said ED' signal, said data and said external error check code for generating a first internal error check code and storing said data and said external error check code in said memory during said storing cycle and for generating a second internal error check code and reading said data and said external error check code from said memory to said output buffer during said reading cycle when both said ED signal and said ED' signal are low; and means, including comparing means, responsive to said ED signal, said ED' signal, said external error check code, said first internal error check code and, said second internal error check code for: (a) storing said first internal error check code in said memory during said storing cycle and comparing said first internal error check code stored in said memory and said second internal error check code and reading the results of said comparison to said output buffer during said reading cycle when said ED signal is high and said ED' signal is low; and (b) storing said external error check in said memory during said storing cycle and comparing said external error check code stored in said memory and an external error check code received from said external source and reading the results of said comparison to said output buffer during said reading cycle when both said ED and said ED' signals are high.