US4077028A
Expired / Lapsed
US
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Error checking and correcting device
Assignee: NCR Voyix Corp
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Filing: 1976-06-14
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Granted: 1978-02-28
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Expires: 1996-06-14
Abstract
Abstract An error checking and correcting device for providing group error detection in addition to single error correction and double error detection in a codeword transmitted through a modular communication channel is disclosed. The codeword comprises a plurality of data bits and a plurality of check bits. The modular communication channel comprises a plurality of modules in each of which a group (or cluster) of bits are transferred in parallel. In the preferred embodiment, the code word contains 40 bits with 32 data bits and 8 check bits, and the modular communication channel is a computer memory comprising 10 modules with 4 bits per module. At the transmitter, the check bit generator generates the check bits from the data bits in accordance with an H-matrix which is partitioned into h-submatrices corresponding to group boundaries of the memory. The construction of the h-submatrices is in accordance with rules necessary for group error detection in addition to single error correction and double error detection. The check bits are appended to the data bits to form a 40 bit code word which is transmitted through the modular memory. At the receiver, a syndrome bit generator generates 8 syndrome bits from the received code word in accordance with the H-matrix. The output of the syndrome bit generator is coupled to both the error detection circuit and the error location circuit. Should a group in the memory be faulty in the process of transmission resulting in a number of bits in the group being in error, logic means are provided in the error detection circuit to identify correctable good data from uncorrectable bad data. According to the syndrome pattern the error detection circuit permits the utilization of received data if no error is detected, or enables the error location circuit to provide single error correction if a single error is detected; or sets an error flag to prohibit the utilization of received data if a random double error is detected or a plurality of errors in the same group are detected.
Inventors
- 👤 Albert S. Lui
- 👤 Majid Arbab
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:49
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1028
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
210 words
A system for providing single error correction, double error detection, and group error detection in a code word having plural groups of information and check bits, which comprises: generator means receiving said code word for generating a plurality of syndrome bits, first circuit means coupled to the output of said generator means for generating a first error signal if the informational content of said syndrome bits indicates a detection of any error in the transmission of said code word, second circuit means coupled to the output of said generator means for generating a second error signal if the informational content of said syndrome bits indicates a detection of two random errors in said code word or an even number of errors in one of said plural groups, third circuit means coupled to the output of said generator means for generating a third error signal if the informational content of said syndrome bits indicates a detection of an odd number of errors greater than one in one of said plural groups, and error location circuit means in electrical communication with said generator means and said first, said second, and said third circuit means for providing an error correction in response to the detection of a single error in said code word.
Claim 2
Independent Claim
210 words
A system for providing single error correction, double error detection, and group error detection in a code word having plural groups of information and check bits, which comprises: generator means receiving said code word for generating a plurality of syndrome bits, first circuit means coupled to the output of said generator means for generating a first error signal if the informational content of said syndrome bits indicates a detection of any error in the transmission of said code word, second circuit means coupled to the output of said generator means for generating a second error signal if the informational content of said syndrome bits indicates a detection of two random errors in said code word or an even number of errors in one of said plural groups, third circuit means coupled to the output of said generator means for generating a third error signal if the informational content of said syndrome bits indicates a detection of an odd number of errors greater than one in one of said plural groups, and error location circuit means in electrical communication with said generator means and said first, said second, and said third circuit means for providing an error correction in response to the detection of a single error in said code word.
Claim 3
Dependent Claim
31 words
The system as described in claim 1 and wherein said first circuit means includes OR gate means coupled to the output of said generator means for generating said first error signal.
Claim 4
Dependent Claim
32 words
The system as described in claim 1 and wherein said second circuit means includes EXCLUSIVE OR gate means coupled to the output of said generator means for generating said second error signal.
Claim 5
Dependent Claim
86 words
The system as described in claim 1 and wherein said third circuit means includes AND gate means and OR gate means, said AND gate means having inputs coupled to said generator means and having outputs coupled to said OR gate means, said OR gate means having first and second outputs with said first output for providing said third error signal and said second output being coupled to said error location circuit means for disabling said error location circuit means in response to said third error signal.
Claim 6
Dependent Claim
142 words
The system as described in claim 1 and wherein said second circuit means includes EXCLUSIVE OR gate means coupled to the output of said generator means for generating said second error signal, and said third circuit means includes AND gate means and OR gate means, said AND gate means and said EXCLUSIVE OR gate means having outputs coupled to the inputs of said OR gate means, said OR gate means having first and second outputs with said first output for providing an error signal if the informational content of said syndrome bits indicates a detection of said two random errors or a plurality of errors in one of said plural groups and said second output being coupled to said error location circuit means for disabling said error location circuit means if said two random errors or said plurality of errors are detected.
Claim 7
Dependent Claim
64 words
The system as described in claim 1, and further including OR gate means in electrical communication with said third circuit means and said error location circuit means, said OR gate means having first and second outputs with said first output for providing said third error signal and said second output for disabling said error location circuit means in response to said third error signal.
Claim 8
Dependent Claim
126 words
The system as described in claim 1 and wherein said second circuit means includes EXCLUSIVE OR gate means coupled to the output of said generator means for generating said second error signal, and Or gate means coupled to the output of said second circuit means and to the output of said third circuit means, said OR gate means having first and second outputs with said first output for providing an error indication if the informational content of said syndrome bits indicates a detection of said two random errors or a plurality of errors in one of said plural groups and said second output being inverted and coupled to said error location circuit means for disabling said error location circuit means in response to said error indication.
Claim 9
Dependent Claim
158 words
An error detection and correction system, which comprises: a. first generator means receiving an information bit stream for providing check bits to form a code word of plural bit groups in accordance with an H-matrix, said H-matrix having a bit structure partitioned to correspond with the boundaries of said plural bit groups and patterned to accommodate the correction of said code word if the presence of only one error is detected and to accommodate the detection of two random errors in said code word and plural errors occurring in one of said plural bit groups; b. second generator means in electrical communication with said first generator means for operating upon said code word in accordance with said H-matrix to provide syndrome bits; and c. logic means responsive to said syndrome bits and in electrical communication with said first generator means for correcting said one error and signalling the occurrence of said plural errors and said two random errors.
Claim 10
Dependent Claim
158 words
An error detection and correction system, which comprises: a. first generator means receiving an information bit stream for providing check bits to form a code word of plural bit groups in accordance with an H-matrix, said H-matrix having a bit structure partitioned to correspond with the boundaries of said plural bit groups and patterned to accommodate the correction of said code word if the presence of only one error is detected and to accommodate the detection of two random errors in said code word and plural errors occurring in one of said plural bit groups; b. second generator means in electrical communication with said first generator means for operating upon said code word in accordance with said H-matrix to provide syndrome bits; and c. logic means responsive to said syndrome bits and in electrical communication with said first generator means for correcting said one error and signalling the occurrence of said plural errors and said two random errors.
Claim 11
Dependent Claim
41 words
The system as described in claim 8 and wherein said first generator means includes a plurality of EXCLUSIVE OR gates for providing check bits by odd parity binary addition of a predetermined combination of information bits in accordance with said H-matrix.
Claim 12
Dependent Claim
44 words
The system as described in claim 8 and wherein said second generator means includes a plurality of EXCLUSIVE OR gates for providing syndrome bits by odd parity binary addition of a predetermined combination of information bits and check bits in accordance with said H-matrix.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-27 | 1981-08-29 | 1982-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-27 | 1985-08-29 | 1986-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-27 | 1989-08-29 | 1990-02-28 | $7700.00 | Window Closed / Lapsed |