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US5515539A
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US
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Apparatus and method for reducing power consumption by peripheral devices after downloading a program therefrom
Assignee: Mitsubishi Electric Corp
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Filing: 1994-06-08
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Granted: 1996-05-07
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Expires: 2014-06-08
Abstract
Abstract A microcomputer system of the present invention, includes for reducing power consumption therein, an internal memory device in a processor device and a buffer, the buffer further including therein disconnection means for connection and disconnection with and from an external bus and power consumption reduction means for reducing power consumption in peripheral device. Hereby, a program that is executable only within the processor device is stored in the internal memory device, and the peripheral devices are brought into a low power consumption mode and the external bus is made disconnectable upon execution of the program.
Inventors
- 👤 Shinichiro Ohashi
- 👤 Kunihiro Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:50
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3234; G06F1/325; G06F1/3275; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
251 words
A microcomputer system having a plurality of peripherals, the system comprising: a microprocessor unit having an internal memory; an external bus, coupled to said microprocessor unit and to the plurality of peripherals; means, coupled to the plurality of peripherals, for reading a program from one of the plurality of peripherals; means, coupled to said internal memory and to said reading means, for storing said program into said internal memory; means, coupled between each of the plurality of peripherals and an input power supply for the plurality of peripherals, for switching an input power voltage of each of the plurality of peripherals to a power saving mode responsive to a first switch instruction from said multiprocessing unit and responsive to completion of said storing means storing said program; means, coupled to said external bus and to said microprocessor unit, for disconnecting said external bus from said microprocessor unit responsive to a disconnect instruction from said multiprocessing unit and responsive to said switching means switching said input power voltage; means, coupled to said internal memory, for executing said program stored in said internal memory; means, coupled to said external bus and to said microprocessor unit, for connecting said external bus to said microprocessor unit responsive to a connect instruction from said multiprocessing unit; and means, coupled to the plurality of peripherals and to said input power supply, for switching said input power supply for the plurality of peripherals to an operating power mode responsive to a second switch instruction from said microprocessing unit.
Claim 2
Dependent Claim
251 words
A microcomputer system having a plurality of peripherals, the system comprising: a microprocessor unit having an internal memory; an external bus, coupled to said microprocessor unit and to the plurality of peripherals; means, coupled to the plurality of peripherals, for reading a program from one of the plurality of peripherals; means, coupled to said internal memory and to said reading means, for storing said program into said internal memory; means, coupled between each of the plurality of peripherals and an input power supply for the plurality of peripherals, for switching an input power voltage of each of the plurality of peripherals to a power saving mode responsive to a first switch instruction from said multiprocessing unit and responsive to completion of said storing means storing said program; means, coupled to said external bus and to said microprocessor unit, for disconnecting said external bus from said microprocessor unit responsive to a disconnect instruction from said multiprocessing unit and responsive to said switching means switching said input power voltage; means, coupled to said internal memory, for executing said program stored in said internal memory; means, coupled to said external bus and to said microprocessor unit, for connecting said external bus to said microprocessor unit responsive to a connect instruction from said multiprocessing unit; and means, coupled to the plurality of peripherals and to said input power supply, for switching said input power supply for the plurality of peripherals to an operating power mode responsive to a second switch instruction from said microprocessing unit.
Claim 3
Independent Claim
151 words
A method for reducing input power consumption of peripheral devices in a microcomputer system, comprising the steps of: reading a program from one of the peripheral devices that is coupled to an external bus of the microcomputer system; storing said program in an internal memory of a microprocessing unit; switching the peripheral devices to a low power consumption voltage responsive to a first switch instruction received from said microprocessing unit and responsive to completion of said program storing step; disconnecting said external bus from said microprocessing unit responsive to a disconnect instruction received from said microprocessing unit received after completion of said low power consumption switching step; executing said program within said microprocessing unit; connecting said external bus to said microprocessing unit responsive to a connect instruction from said microprocessing unit; and switching the peripheral devices to an operating power voltage responsive to a second switch instruction from said microprocessing unit.
Claim 4
Independent Claim
151 words
A method for reducing input power consumption of peripheral devices in a microcomputer system, comprising the steps of: reading a program from one of the peripheral devices that is coupled to an external bus of the microcomputer system; storing said program in an internal memory of a microprocessing unit; switching the peripheral devices to a low power consumption voltage responsive to a first switch instruction received from said microprocessing unit and responsive to completion of said program storing step; disconnecting said external bus from said microprocessing unit responsive to a disconnect instruction received from said microprocessing unit received after completion of said low power consumption switching step; executing said program within said microprocessing unit; connecting said external bus to said microprocessing unit responsive to a connect instruction from said microprocessing unit; and switching the peripheral devices to an operating power voltage responsive to a second switch instruction from said microprocessing unit.
Claim 5
Dependent Claim
213 words
A microcomputer system, comprising: a microprocessing unit including a central processing unit, an internal memory, and a buffer wherein said central processing unit is coupled to said internal memory and to said buffer by an internal bus and said buffer includes means, responsive to instructions from said central processing unit, for disconnecting and connecting an external bus; an external bus coupled to said buffer; a first peripheral device, coupled to said external bus, for interfacing to said microprocessing unit, said first peripheral device operational when supplied with a first voltage level and non-operational when supplied with a second voltage level less than said first voltage level; switching means, coupled to said first peripheral device and to a power supply, for providing said first peripheral device with said first voltage level in response to a first signal and with said second voltage level responsive to a second signal; and power consumption reduction means, coupled to said external bus and responsive to instructions from said central processing unit, for asserting said first signal and said second signal wherein said second signal is asserted after data is read into said buffer over said external bus and wherein said means for connecting and disconnecting disconnects said buffer from said external bus after said second signal is asserted.
Claim 6
Dependent Claim
213 words
A microcomputer system, comprising: a microprocessing unit including a central processing unit, an internal memory, and a buffer wherein said central processing unit is coupled to said internal memory and to said buffer by an internal bus and said buffer includes means, responsive to instructions from said central processing unit, for disconnecting and connecting an external bus; an external bus coupled to said buffer; a first peripheral device, coupled to said external bus, for interfacing to said microprocessing unit, said first peripheral device operational when supplied with a first voltage level and non-operational when supplied with a second voltage level less than said first voltage level; switching means, coupled to said first peripheral device and to a power supply, for providing said first peripheral device with said first voltage level in response to a first signal and with said second voltage level responsive to a second signal; and power consumption reduction means, coupled to said external bus and responsive to instructions from said central processing unit, for asserting said first signal and said second signal wherein said second signal is asserted after data is read into said buffer over said external bus and wherein said means for connecting and disconnecting disconnects said buffer from said external bus after said second signal is asserted.
Claim 7
Dependent Claim
22 words
The microcomputer system of claim 3 wherein said first peripheral device is a ROM and said second voltage level is zero volts.
Claim 8
Dependent Claim
83 words
The microcomputer system of claim 3 further comprising a second peripheral device coupled to said external bus, said second peripheral device operational when supplied with a third voltage level and non-operational when supplied with a fourth voltage level less than said third voltage level, and wherein: said switching means, coupled to said second peripheral device, provides said second peripheral device with said third voltage level in response to said first signal and said fourth voltage level in response to said second voltage level.
Claim 9
Dependent Claim
22 words
The microcomputer system of claim 5 wherein said first peripheral device is a ROM and said second voltage level is zero volts.
Claim 10
Dependent Claim
32 words
The microcomputer system of claim 6 wherein said second peripheral device is a RAM and said fourth voltage level is greater than zero volts and sufficient to inhibit volatility of stored information.
Claim 11
Dependent Claim
18 words
The microcomputer system of claim 7 wherein said first voltage level and said third voltage level are equal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |