Microcomputer system with dual DMA mode transmissions

Claim 1

A microcomputer system comprising: (a) an input/output device having a first line for outputting an interrupt request signal and a second line for outputting a data transmission request signal indicative of whether or not data transmission in a DMA mode is requested; (b) interface means; (c) a bus system connected to the input/output device via the interface means; (d) a memory connected to the bus system for data transmission to or from the input/output device; (e) a CPU capable of being electrically coupled to the bus system for data transmission between the input/output device and the memory in a programmed CPU mode, and of being uncoupled from the bus system for data transmission therebetween in the DMA mode, so that data transmission is possible in a cycle steal mode, in which the DMA transmission and the programmed CPU transmission alternate, by periodically coupling the uncoupling the CPU to and from the bus system, the CPU comprising: (1) a first terminal for inputting a modified hold request signal which commands the coupling and uncoupling of the CPU to and from the bus system; (2) a second terminal for outputting a hold acknowledge signal indicative of whether the CPU is coupled to or uncoupled from the bus system; (3) a third terminal for outputting a halt signal indicative of whether the CPU is active or inactive, the halt signal having a first state indicative of which the CPU is active and a second state indicative of which the CPU is inactive; and (4) A fourth terminal connected to the first line of the input/output device for inputting the interrupt request signal which commands the CPU to become active; and (f) a DMA controller connected to the bus system and to the CPU for controlling data transmission between the input/output device and the memory, the DMA controller comprising: (1) a first terminal connected to the second line of the input/output device for receiving therefrom a data transmission request signal; (2) a second terminal connected to the third terminal of the CPU for inputting the halt signal; and (3) a third terminal connected to the second terminal of the CPU for inputting the hold acknowledge signal; (4) a fourth terminal connected to the first terminal of the CPU for outputting the modified hold request signal; and (5) a modified hold request signal generator circuit connected between the first and second terminals and fourth terminal of the DMA controller for generating and delivering the modified hold request signal to the CPU in order to cause the same to be controllably coupled to and uncoupled from the bus system, the modified hold request signal generator circuit being responsive to both the data transmission request signal and the halt signal for causing the CPU to be periodically coupled to and uncoupled from the bus system for data transmission in the cycle steal mode if the CPU is active, and as long as the CPU remains so, when DMA data transmission is requested by the data transmission request signal, and for causing the CPU to remain uncoupled from the bus system for data transmission in a sustained DMA mode if the CPU is inactive, and as long as the CPU remains so, when DMA data transmission is requested by the data transmission request signal.