Processor device

Claim 2

A processor device comprising a direct memory access controller utilizing a common memory bus for executing an operation of a direct memory access mode for gaining access to a main memory, a central processing unit utilizing said common memory bus for executing an operation of a microprogram-executing mode for gaining access to microprogram data stored in the main memory, and a microprogram controller connected to said direct memory access controller and said central processing unit for storing microprogram data to control the operation of the direct memory access controller and the central processing unit so that the microprogram controller will instruct the direct memory access controller and the central processing unit with respect to the execution of the operation of the direct memory access mode and microprogram-executing mode, the direct memory access controller, central processing unit and microprogram controller being integrated in a single semiconductor chip.

Claim 3

The processor device according to claim 1, wherein the direct memory access controller is provided with means for effecting a changeover between the direct memory access mode and microprogram-executing mode relative to the exclusive use of the common memory bus.

Claim 4

The processor device according to claim 2, wherein said changeover means comprises a bus controller.

Claim 5

The processor device according to claim 1, wherein the direct memory access controller includes a cycle steal controlling means relative to the main memory.

Claim 6

The processor device according to claim 4, wherein said cycle steal controlling means includes a microprogram portion for storing microprogram data and a bus controller for controlling the exclusive use of the common memory bus connected to the main memory, wherein, when the bus controller receives a bus request signal from the microprogram portin, a common memory bus available permit signal is given to the direct memory access controller whereby the direct memory access controller executes access to the main memory utilizing an idle time of the common memory bus unoccupied by the central processing unit.

Claim 7

The processor device according to claim 1, wherein said microprogram controller includes means for storing sequence microprogram data for controlling the direct memory access controller and central processing unit, means for supplying bus request signals corresponding to the direct memory access mode and microprogram-executing mode according to the microprogram to the bus controller for controlling the common bus, and means for generating the request signal before a need for the direct memory access mode arises.

Claim 8

A processor device comprising a direct memory access controller utilizing a common memory bus for executing an operation of a direct memory access mode for gaining access to a main memory and including a bus controller for effecting a changeover between a direct memory access mode and microprogram-executing mode relative to the exclusive use of the common memory bus, a counter connected to an output terminal of the bus controller to effect an address step and an address register connected to the counter to store address data, a central processing unit utilizing said common memory bus for executing an operation of a microprogram-executing mode for gaining access to microprogram data stored in the main memory and including a register group connected to an output terminal of the bus controller to store address data for calculation and an arithmetic logic unit connected to said register group for executing an arithmetic logic operation based on predetermined data, and a microprogram controller connected to the direct memory access controller and central processing unit for storing microprogram data to control the direct memory access controller and control processing unit so that the microprogram controller will instruct the direct memory access controller and the central processing unit with respect to the execution of the operation of the direct memory access mode and microprogram-executing mode.

Claim 9

A processor device comprising a direct memory access controller utilizing a common memory bus for executing an operation of a direct memory access mode for gaining access to a main memory and including a bus controller for effecting a changeover between a direct memory access mode and microprogram-executing mode relative to the exclusive use of the common memory bus, a counter connected to an output terminal of the bus controller to effect an address step and an address register connected to the counter to store address data, a central processing unit utilizing said common memory bus for executing an operation of a microprogram-executing mode for gaining access to microprogram data stored in the main memory and including a register group connected to an output terminal of the bus controller to store address data for calculation and an arithmetic logic unit connected to said register group for executing an arithmetic logic operation based on predetermined data, and a microprogram controller connected to the direct memory access controller and central processing unit for storing microprogram data to control the direct memory access controller and control processing unit so that the microprogram controller will instruct the direct memory access controller and the central processing unit with respect to the execution of the operation of the direct memory access mode and microprogram-executing mode.

Claim 10

The processor device according to claim 7, wherein said direct memory access controller, said central processing unit, and said microprogram controller are integrated in a single chip.