US4417304A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit
Assignee: International Business Machines Corp
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Filing: 1981-11-13
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Granted: 1983-11-22
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Expires: 2001-11-13
Abstract
Abstract A cycle steal mechanism for enabling a host processor to initiate and control the cycle stealing of data to or from a storage unit located in an I/O controller which is connected to the I/O channel bus of the host processor. The I/O controller also includes a microprocessor and a direct memory access (DMA) unit either or both of which can be used to control the transfer of data between the I/O controller storage unit and the host processor. Typically, the DMA unit is used for cycle stealing data between the controller storage unit and the host processor. The cycle steal mechanism of the present invention enables the host processor to also initiate and control the cycle stealing of data to or from the controller storage unit without interrupting the program running in the controller microprocessor and without interrupting the cycle stealing operations of the DMA unit. This new cycle steal mechanism is the reverse of the normal situation where it is the microprocessor or DMA unit that is controlling the cycle stealing. Since the I/O controller accommodates both kinds of cycle stealing, the present invention can be said to provide a "2-way" cycle stealing capability. Not only can the I/O controller cycle steal data to or from the host processor main storage unit, but also the host processor can cycle steal data to or from the I/O controller storage unit. The cycle stealing by the host processor is transparent to both the microprocessor and the DMA unit in the I/O controller. This new cycle steal mechanism makes use of the microprocessor address set-up pulse (ALE) and the DMA unit address set-up pulse (ADSTB) to cause the cycle stealing of the data to or from the controller storage unit to occur during such address set-up time. These address set-up times are times when neither the microprocessor nor the DMA unit is actually moving data into or out of the storage unit in the I/O controller.
Inventors
- 👤 John M. Dinwiddie, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:20
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
222 words
In a data processing system having a processor unit and a random access storage unit associated with and coupled to it and wherein the processor unit provides for each of its machine cycles an address set-up indicative pulse denoting the occurrence of a processor address set-up interval during a portion of each machine cycle, a cycle steal mechanism for transferring data between a separate data handling unit and the processor storage unit without interrupting a program being executed by the processor unit and comprising: selectively operable signal transfer circuitry for transferring address bits from the data handling unit to the address terminals of the processor storage unit and for providing a data transfer path between the data handling unit and the data terminals of the processor storage unit; and cycle steal control circuitry responsive to the occurrence of both a transfer request indicative signal from the data handling unit and an address set-up indicative pulse from the processor unit for activating during the processor address set-up interval of the processor machine cycle the selectively operable signal transfer circuitry for enabling the transfer of data from the data handling unit to the processor storage unit or vice versa during a portion of the processor machine cycle when the processor unit itself is not actually moving data to or from the processor storage unit.
Claim 2
Dependent Claim
222 words
In a data processing system having a processor unit and a random access storage unit associated with and coupled to it and wherein the processor unit provides for each of its machine cycles an address set-up indicative pulse denoting the occurrence of a processor address set-up interval during a portion of each machine cycle, a cycle steal mechanism for transferring data between a separate data handling unit and the processor storage unit without interrupting a program being executed by the processor unit and comprising: selectively operable signal transfer circuitry for transferring address bits from the data handling unit to the address terminals of the processor storage unit and for providing a data transfer path between the data handling unit and the data terminals of the processor storage unit; and cycle steal control circuitry responsive to the occurrence of both a transfer request indicative signal from the data handling unit and an address set-up indicative pulse from the processor unit for activating during the processor address set-up interval of the processor machine cycle the selectively operable signal transfer circuitry for enabling the transfer of data from the data handling unit to the processor storage unit or vice versa during a portion of the processor machine cycle when the processor unit itself is not actually moving data to or from the processor storage unit.
Claim 3
Dependent Claim
20 words
A cycle steal mechanism in accordance with claim 1 wherein the separate data handling unit is a second processor unit.
Claim 4
Dependent Claim
16 words
A cycle steal mechanism in accordance with claim 1 wherein the processor unit is a microprocessor.
Claim 5
Dependent Claim
36 words
A cycle steal mechanism in accordance with claim 3 wherein the address set-up indicative pulse is an address latch enable pulse developed by the microprocessor for only a portion of each operating cycle of the microprocessor.
Claim 6
Dependent Claim
20 words
A cycle steal mechanism in accordance with claim 4 wherein the separate data handling unit is a second processor unit.
Claim 7
Dependent Claim
142 words
A cycle steal mechanism in accordance with claim 1 wherein: the data processing system further includes a direct memory access controller for accessing the storage unit, for generating for a portion of each of its access cycles an address set-up indicative pulse denoting the occurrence of its address set-up interval and for supplying a hold signal to the processor unit for placing it in a hold state during the storage accessing operation of the direct memory access controller; and the cycle steal control circuitry is responsive to the occurrence of both a transfer request indicative signal from the data handling unit and an address set-up indicative pulse from either the processor unit or the direct memory access controller for activating the selectively operable signal transfer circuitry during the address set-up interval of either the processor unit or the direct memory access controller.
Claim 8
Dependent Claim
135 words
A cycle steal mechanism in accordance with claim 1 wherein: the minimum access time of the processor storage unit is greater than the processor address set-up interval; the cycle steal control circuitry includes circuitry for producing an external READY signal and supplying it to the processor unit; the processor unit also includes circuitry responsive to the absence of the external READY signal for placing the processor unit in a wait state; the cycle steal control circuitry commences activating the signal transfer circuitry during the processor address set-up interval and continues such activation to provide at least the minimum access time for the processor storage unit; and the cycle steal control circuitry includes circuitry for removing the external READY signal from the processor unit for the length of time that the signal transfer circuitry is activated.
Claim 9
Dependent Claim
167 words
A cycle steal mechanism in accordance with claim 7 wherein: the data processing system further includes a direct memory access controller for accessing the storage unit, for generating for a portion of each of its access cycles an address set-up indicative pulse denoting the occurrence of its address set-up interval and for supplying a hold signal to the processor unit for placing it in a hold state during the storage accessing operation of the direct memory access controller, such direct memory access controller further including circuitry responsive to the absence of an external READY signal for placing the controller in a wait state; the cycle steal control circuitry commences activating the signal transfer circuitry during the address set-up interval or either the processor unit or the direct memory access controller; and the cycle steal control circuitry includes circuitry for removing the external READY signal from both the processor unit and the direct memory access controller for the length of time that the signal transfer circuitry is activated.
Claim 10
Dependent Claim
229 words
In a data processing system having a microprocessor and a random access storage unit associated with and coupled to it and wherein the microprocessor provides for only a portion of each of its operating cycles an address set-up indicative pulse denoting the occurrence of a microprocessor address set-up interval, a cycle steal mechanism for transferring data between a second processor and the microprocessor storage unit without interrupting a program being executed by the microprocessor and comprising: selectively operable signal transfer circuitry for transferring address bits from the second processor to the address terminals of the microprocessor storage unit and for providing a data transfer path between the second processor and the data terminals of the microprocessor storage unit; address decoder circuitry responsive to the occurrence of predetermined address bits from the second processor for producing an address capture signal; and cycle steal control circuitry responsive to the occurrence of both an address capture signal from the address decoder circuitry and an address set-up indicative pulse from the microprocessor for activating during the microprocessor address set-up interval of the microprocessor operating cycle the selectively operable signal transfer circuitry for enabling the transfer of data from the second processor to the microprocessor storage unit or vice versa during a portion of the microprocessor operating cycle when the microprocessor itself is not actually moving data to or from the microprocessor storage unit.
Claim 11
Dependent Claim
229 words
In a data processing system having a microprocessor and a random access storage unit associated with and coupled to it and wherein the microprocessor provides for only a portion of each of its operating cycles an address set-up indicative pulse denoting the occurrence of a microprocessor address set-up interval, a cycle steal mechanism for transferring data between a second processor and the microprocessor storage unit without interrupting a program being executed by the microprocessor and comprising: selectively operable signal transfer circuitry for transferring address bits from the second processor to the address terminals of the microprocessor storage unit and for providing a data transfer path between the second processor and the data terminals of the microprocessor storage unit; address decoder circuitry responsive to the occurrence of predetermined address bits from the second processor for producing an address capture signal; and cycle steal control circuitry responsive to the occurrence of both an address capture signal from the address decoder circuitry and an address set-up indicative pulse from the microprocessor for activating during the microprocessor address set-up interval of the microprocessor operating cycle the selectively operable signal transfer circuitry for enabling the transfer of data from the second processor to the microprocessor storage unit or vice versa during a portion of the microprocessor operating cycle when the microprocessor itself is not actually moving data to or from the microprocessor storage unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-21 | 1987-05-23 | 1987-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-21 | 1991-05-23 | 1991-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-21 | 1995-05-23 | 1995-11-22 | $7700.00 | Window Closed / Lapsed |