Internal low voltage transformation circuit of static random access memory

Claim 1

A static random access memory comprising: a plurality of memory cells, each memory cell having an operating mode and a standby mode and including a flipflop circuit and a pair of word transistors, each word transistor having a gate electrode, a pair of bit lines in which each bit line is connected to a respective word transistor of each of the pairs of word transistors, a word line connected to said gate electrode of each of said pairs of word transistors, and internal low voltage supply means including a reference voltage supply circuit and an internal voltage control circuit for supplying an internal low voltage pulled down from a power source voltage to said plurality of memory cells in said operating mode, said internal low voltage supply means setting said reference voltage supply circuit and said internal voltage control circuit to an off state in said standby mode, said internal low voltage supply means further including voltage pull-down means for supplying a data hold voltage to said plurality of memory cells in said standby mode and having a power consumption lower than that of a circuit including said reference voltage supply circuit and said internal voltage control circuit in an on state.