Static semiconductor memory device comprising word lines each operating at three different voltage levels

Claim 2

A semiconductor memory device having a plurality of memory cells connected respectively to a plurality of word lines, operable in a read mode and a write mode according to a write enable signal, said device comprising: decoder means (1 and 2) for decoding an applied address signal to select an associated word line, word line level generating means (40) responsive to said address signal and said write enable signal for generating a signal at any one of a high level, a low level and an intermediate level between said high level and said low level, said level changing according to the writing and the reading of a selected memory cell, said word line level generating means generating said intermediate level signal for the word line when the word line is selected for a write operation, and means (10 and 12) provided between said decoder means (1 and 2) and said plurality of word lines for transmitting said signal from said word line level generating means to said selected word line.

Claim 3

A semiconductor memory device as set forth in claim 1 wherein said word line level generating means comprises: address change detecting means (30 and 31) for detecting a change in the applied address signal, control signal generating means (32) for generating first and second control signals changing in response to the signal from said address change detecting means and said write enable signal, and a word line level signal generating circuit (4) responsive to said first and second control signals for generating said signal at any one of said high level, said low level and said intermediate level between said high level and said low level.

Claim 4

A semiconductor memory device as set forth in claim 1, wherein said signal level transmitting means is an inverter provided between said decoder means and said word line, and the signal from said word line level generating means (40) is applied to one input terminal of a transistor of said inverter.

Claim 5

A semiconductor memory device as set forth in claim 2, wherein each of said plurality of word lines is connected with a MOS transistor for pulling down a word line signal level, and a signal as a logical product of said first and second control signals is applied to the gate of said pull-down MOS transistor.

Claim 6

A semiconductor memory device as set forth in claim 1, wherein the signal from said word line level generating means changes to said relatively high level at the time of reading of a selected memory cell.

Claim 7

A semiconductor memory device as set forth in claim 1, wherein said semiconductor memory device is a static RAM.

Claim 8

A semiconductor memory device as recited in claim 2, wherein said address change detecting means includes a plurality of address transition detection means each connected for detecting transitions in address signals provided by said decoder means, each of said address transition detection means providing an output signal, an OR gating means having a plurality of inputs, each input connected to a respective output of one of said address transition detection means, said OR gate means providing an output signal to said control signal generating means.

Claim 9

A semiconductor memory device as recited in claim 7 further comprising AND gate means connected to receive said first and second control signals generated by said control signal generating means for providing an output signal for connection to a MOS pull-down transistor for pulling down a word line signal level in response to detection of a logical product of said first and second control signals.

Claim 10

In a semiconductor memory device having a plurality of memory cells connected respectively to a plurality of word lines, operable in a read mode and a write mode according to a write enable signal, the improvement comprising: decoder means (1 and 2) for decoding an applied address signal to select an associated word line, word line level generating means 40) responsive to said address signal and said write enable signal for generating a signal for selected word lines, said word line level generating means generating said signal at three levels, including a high level, a low level and an intermediate level between said high level and said low level, said signal generated at levels which are different for word lines selected for writing of a selected memory cell and for word lines selected for reading of a selected memory cell, said word line level generating means generating said intermediate level signal when the word line is selected for a write operation, and means (10 and 20) provided between said decoder means (1 and 2) and said plurality of word lines for transmitting said signal from said word line level generating means to said selected word line.

Claim 11

In a semiconductor memory device having a plurality of memory cells connected respectively to a plurality of word lines, operable in a read mode and a write mode according to a write enable signal, the improvement comprising: decoder means (1 and 2) for decoding an applied address signal to select an associated word line, word line level generating means 40) responsive to said address signal and said write enable signal for generating a signal for selected word lines, said word line level generating means generating said signal at three levels, including a high level, a low level and an intermediate level between said high level and said low level, said signal generated at levels which are different for word lines selected for writing of a selected memory cell and for word lines selected for reading of a selected memory cell, said word line level generating means generating said intermediate level signal when the word line is selected for a write operation, and means (10 and 20) provided between said decoder means (1 and 2) and said plurality of word lines for transmitting said signal from said word line level generating means to said selected word line.

Claim 12

A semiconductor memory device having a plurality of memory cells connected respectively to a plurality of word lines, operable in a read mode and a write mode according to a write enable signal, said device comprising: decoder means (1 and 2) for decoding an applied address signal to select an associated word line, word line level generating means (40) responsive to said address signal and said write enable signal for generating a signal for a selected word line, and means (10 and 20) provided between said decoder means (1 and 2) and said plurality of word lines for transmitting said signal from said word line level generating means to said selected word line, said word line level generating means comprising potential reducing means for reducing a potential difference between a selected word line and non selected word lines thereby reducing current flow through non selected memory cells connected to a selected word line, said potential reducing means comprises means for providing three different signal levels to said selected word line including an intermediate level between first and second levels, said intermediate level provided when said word line is selected for a write operation to a selected memory cell.

Claim 13

A semiconductor memory device having a plurality of memory cells connected respectively to a plurality of word lines, operable in a read mode and a write mode according to a write enable signal, said device comprising: decoder means (1 and 2) for decoding an applied address signal to select an associated word line, word line level generating means (40) responsive to said address signal and said write enable signal for generating a signal for a selected word line, and means (10 and 20) provided between said decoder means (1 and 2) and said plurality of word lines for transmitting said signal from said word line level generating means to said selected word line, said word line level generating means comprising potential reducing means for reducing a potential difference between a selected word line and non selected word lines thereby reducing current flow through non selected memory cells connected to a selected word line, said potential reducing means comprises means for providing three different signal levels to said selected word line including an intermediate level between first and second levels, said intermediate level provided when said word line is selected for a write operation to a selected memory cell.

Claim 14

A semiconduotor memory device as recited in claim 10 wherein said means for providing different signal levels is operable for providing different signal levels to said selected word line during a write mode operation than during a read mode operation.

Claim 15

A semiconductor memory device as recited in claim 11 wherein said means for providing different signal levels is operable for providing a lower signal level to said selected word line during a write mode operation than during a read mode operation.

Claim 16

A semiconductor memory device as recited in claim 11 wherein said potential reducing means is operable for reducing the potential difference between the selected and unselected word lines during a write mode operation relative to a potential difference during a read mode operation.

Claim 17

A semiconductor memory device as recited in claim 11 wherein said means for providing different signal levels is operable for providing said first level to a selected word line when said word line is selected for a read operation from a selected memory cell, and for providing said second level to said word line when said word line is not selected.

Claim 18

A semiconductor memory device as recited in claim 11 wherein said means for providing different signal levels is operable for providing said first level to a selected word line during a read operation, and for providing said second level to said word line when said read operation is concluded.

Claim 19

A semiconductor memory device as recited in claim 15 wherein said means for providing different signal levels is further operable for providing to a selected word line said second level when said write operation is concluded.

Claim 20

A semiconductor memory device as recited in claim 6 wherein said semiconductor memory device comprises a RAM chip and said word line signal generating circuit is formed of a single means for generating said intermediate level signal for each of said word lines thereof.