Cross-coupled inverters static random access memory

Claim 2

A circuit for driving a MOS transistor circuit by generating an output signal having a voltage higher than the voltage of a power source with a boosting operation of a condenser, comprising: the power source; an output terminal; a first enhancement-type MOS transistor connected between the power source and the output terminal; a first condenser connected to the gate of the enhancement-type MOS transistor; a second enhancement-type MOS transistor connected such that the source and the drain of the second enhancement MOS transistor are coupled to the power source and the gate of the first enhancement-type MOS transistor, and the gate of the second enhancement-type MOS transistor is coupled to the gate of the first enhancement-type MOS transistor; and a second condenser connected to the output terminal.

Claim 3

A static random access memory (RAM) comprising: a flip-flop for storing data, comprising a pair of inverters cross-coupled; a data line; a single transfer gate MOS transistor connected between the flip-flop and the data line; a word line for carrying a signal applied to the gate of the MOS transistor; an enhancement-type MOS transistor connected between a power source of VCC and the word line; a first condenser connected to the gate of the enhancement-type MOS transistor for providing a voltage of (VCC+VTH*), VTH* being a threshold voltage of the enhancement-type MOS transistor, with a boosting operation according to the application of a RAM selection signal, so that the word line bears a voltage similar to that of the power source; a second condenser connected to the word line for providing a voltage VW, which is higher than the voltage of the power source, to the word line with the boosting operation in order to write the data; and a MOS transistor connected such that the source and the drain of the MOS transistor are connected to the power source and the gate of the enhancement-type MOS transistor, and the gate of the MOS transistor is connected to the gate of the enhancement-type MOS transistor.

Claim 4

A static random access memory (RAM) comprising: a flip-flop for storing data, comprising a pair of inverters cross-coupled; a data line; a single transfer gate MOS transistor connected between the flip-flop and the data line; a word line for carrying a signal applied to the gate of the MOS transistor; an enhancement-type MOS transistor connected between a power source of VCC and the word line; a first condenser connected to the gate of the enhancement-type MOS transistor for providing a voltage of (VCC+VTH*), VTH* being a threshold voltage of the enhancement-type MOS transistor, with a boosting operation according to the application of a RAM selection signal, so that the word line bears a voltage similar to that of the power source; a second condenser connected to the word line for providing a voltage VW, which is higher than the voltage of the power source, to the word line with the boosting operation in order to write the data; and a MOS transistor connected such that the source and the drain of the MOS transistor are connected to the power source and the gate of the enhancement-type MOS transistor, and the gate of the MOS transistor is connected to the gate of the enhancement-type MOS transistor.

Claim 5

A static random access memory cell circuit comprising: flip-flop means for storing data therein, said flip-flop means having said data selectively written therein and read therefrom; a single data line transferring data to and from said flip-flop means; a single transistor means, connected between said flip-flop means and said data line, for controlling the transfer of data to and from said flip-flop means, said single transistor means having a control terminal for receiving a control signal; a single word line for supplying said control signal to the control terminal of said single transistor means, said control signal supplied thereby selecting said cell and having a first voltage for enabling the reading of data from said flip-flop means and a second voltage different from said first voltage for writing data into said flip-flop means.

Claim 6

A static random access memory cell circuit comprising: flip-flop means for storing data therein, said flip-flop means having said data selectively written therein and read therefrom; a single data line transferring data to and from said flip-flop means; a single transistor means, connected between said flip-flop means and said data line, for controlling the transfer of data to and from said flip-flop means, said single transistor means having a control terminal for receiving a control signal; a single word line for supplying said control signal to the control terminal of said single transistor means, said control signal supplied thereby selecting said cell and having a first voltage for enabling the reading of data from said flip-flop means and a second voltage different from said first voltage for writing data into said flip-flop means.

Claim 7

The memory cell of claim 3 wherein said flip-flop means comprises a pair of cross-coupled inverters.

Claim 8

The memory cell of claim 4 wherein each of said cross-coupled inverters comprises: an MOS transistor; and a high impedance resistor having a first terminal coupled to said MOS transistor and a second terminal coupled to a source voltage.

Claim 9

The memory cell of claim 4 wherein each of said cross-coupled inverters comprises: a first MOS transistor; and a second MOS transistor of the enhancement type serially connected to said first MOS transistor.

Claim 10

The memory cell of claim 4 wherein each of said cross-coupled inverters comprises: a first MOS transistor; and a second MOS transistor of the depletion type serially connected to said first MOS transistor.

Claim 11

The memory cell of claim 3 wherein said single transistor means is a single MOS transistor.

Claim 12

The memory cell of claim 3 wherein said flip-flop means is disposed between a source voltage and ground, said first voltage being substantially equal to said source voltage.

Claim 13

The memory cell of claim 9 wherein said single transistor means has a threshold voltage which must be supplied to its control terminal to cause conduction between said data line and said flip-flop means; said second voltage being substantially equal to said source voltage plus the threshold voltage of said single transistor means.

Claim 14

The memory cell of claim 4 wherein said single transistor means is a single MOS transistor.

Claim 15

The memory cell of claim 11 wherein said single MOS transistor has a threshold voltage which must be supplied to said control terminal to cause conduction between said data line and said flip-flop means; said second voltage being substantially equal to said source voltage plus the threshold voltage of said single transistor means.

Claim 16

A static random access memory cell circuit consisting essentially of: flip-flop means for storing data therein, said flip-flop means having said data selectively written therein and read therefrom; a single data line transferring data to and from said flip-flop means; a single transistor means, connected between said flip-flop means and said data line, for controlling the transfer of data to and from said flip-flop means, said single transistor means having a control terminal for receiving a control signal; a single word line for supplying said control signal to the control terminal of said single transistor means, said control signal supplied thereby selecting said cell and enabling the reading of data from said flip-flop means and the writing of data into said flip-flop means.

Claim 17

A static random access memory cell circuit consisting essentially of: flip-flop means for storing data therein, said flip-flop means having said data selectively written therein and read therefrom; a single data line transferring data to and from said flip-flop means; a single transistor means, connected between said flip-flop means and said data line, for controlling the transfer of data to and from said flip-flop means, said single transistor means having a control terminal for receiving a control signal; a single word line for supplying said control signal to the control terminal of said single transistor means, said control signal supplied thereby selecting said cell and enabling the reading of data from said flip-flop means and the writing of data into said flip-flop means.

Claim 20

The method of claim 14 wherein said single transistor means is an MOS transistor, said MOS transistor having a threshold voltage which must be supplied to its control terminal to cause conduction thereacross; said random access memory cell being disposed between a source voltage and ground; said first voltage being substantially equal to said source voltage; said second voltage being substantially equal the sum of said source voltage and said threshold voltage.