US4023148A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Write speed-up circuit for integrated data memories
Assignee: International Business Machines Corp
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Filing: 1975-11-26
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Granted: 1977-05-10
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Expires: 1995-11-26
Abstract
Abstract Modern bipolar cross coupled memory cells for high density arrays use diodes as coupling elements from the cell to the bit lines. The write operation of these cells requires a high amount of current if the current gain of the cell transistors is high. The time required to perform a write operation is prolonged significantly due to the inherent capacitors in the cell known as the Miller effect. The described circuit completely eliminates the Miller effect during the write operation and makes the required write current completely independent of the current gain of the cell transistors. In the present invention this is accomplished by dropping the word line of such a cell from a stand-by potential to a select potential, so that the inner cell nodes are equally discharged, without disturbing the state of the cell, after which the word line is pulsed up to an intermediate potential between the select potential and the stand-by potential.
Inventors
- 👤 Klaus Heuber
- 👤 Wilfried Klein
- 👤 Knut Najmann
- 👤 Siegfried K. Wiedmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415; G11C11/411; G11C11/4113
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
160 words
A memory circuit comprising, a word line, a bit line, a memory cell coupled to the word line and the bit line, a voltage selection circuit coupled to said word line comprising first means for setting said word line at a first voltage level having a given magnitude to permit standby current to flow through the cell, second means for setting said word line at a second voltage level having a magnitude lower than the said given magnitude to increase the current flow through the cell to discharge the internal nodes of the cell, and third means for setting said word line at a third voltage level having a magnitude higher than said second magnitude to turn off said cross coupled cell, and means coupled to said bit line for selectively applying a write current to said cell during the application of said third voltage level to said word line to recharge the state of one of said internal nodes.
Claim 2
Dependent Claim
160 words
A memory circuit comprising, a word line, a bit line, a memory cell coupled to the word line and the bit line, a voltage selection circuit coupled to said word line comprising first means for setting said word line at a first voltage level having a given magnitude to permit standby current to flow through the cell, second means for setting said word line at a second voltage level having a magnitude lower than the said given magnitude to increase the current flow through the cell to discharge the internal nodes of the cell, and third means for setting said word line at a third voltage level having a magnitude higher than said second magnitude to turn off said cross coupled cell, and means coupled to said bit line for selectively applying a write current to said cell during the application of said third voltage level to said word line to recharge the state of one of said internal nodes.
Claim 3
Dependent Claim
18 words
The memory of claim 1 wherein said third voltage level is intermediate said first and second voltage levels.
Claim 4
Dependent Claim
36 words
The memory of claim 1 wherein said first means of said voltage selection circuit comprises a voltage source and a first transistor coupling said word line to said voltage source to produce said second voltage level.
Claim 5
Dependent Claim
44 words
The memory of claim 3 wherein said second means of said voltage selection circuit comprises an impedance and a second transistor coupled serially therewith, said impedance and said second transistor coupling said word line to said voltage source to produce said third voltage level.
Claim 6
Dependent Claim
40 words
The memory circuit of claim 4 wherein said first means of said voltage selection circuit comprises a pair of diodes coupled to said voltage source and in parallel with said first and second transistors to produce said first voltage level.
Claim 7
Dependent Claim
28 words
The memory of claim 5 wherein said voltage selection circuit further includes a second voltage source and impedance means coupling said second voltage source to said word line.
Claim 8
Dependent Claim
27 words
The memory circuit of claim 6 wherein said first and second transistors are bipolar transistors and said impedance in series with said second transistor is a diode.
Claim 9
Dependent Claim
13 words
The memory circuit of claim 7 wherein said diode is a Schottky diode.
Claim 10
Dependent Claim
44 words
The memory circuit of claim 1 wherein said memory cell includes a pair of cross coupled bipolar transistors, respective load transistors coupled serially therewith, and a source of predetermined potential, said load transistors coupling said cross coupled transistors to said source of predetermined potential.
Claim 11
Dependent Claim
23 words
The memory circuit of claim 9 wherein said cross coupled bipolar transistors are NPN transistors and said load transistors are bipolar PNP transistors.
Claim 12
Dependent Claim
158 words
A memory circuit coupling, a word line, first and second bit lines, a memory cell comprising a pair of cross coupled bipolar transistors coupled to said word line and coupled between said bit lines, a speed-up circuit coupled to said word line, said speed-up circuit comprising, a first transistor coupling said word line to a voltage source, a second transistor in parallel with said first transistor and in series with an impedance coupling said word line to said voltage source, means for turning on said first transistor to set a first selected voltage level on said word line; and means for turning off said first transistor and turning on said second transistor to set a second selected voltage level on said word line; and means for applying a write current to said cell from one of said bit lines while said second transistor is turned on to set one of said cross coupled transistors in a conductive state.
Claim 13
Dependent Claim
158 words
A memory circuit coupling, a word line, first and second bit lines, a memory cell comprising a pair of cross coupled bipolar transistors coupled to said word line and coupled between said bit lines, a speed-up circuit coupled to said word line, said speed-up circuit comprising, a first transistor coupling said word line to a voltage source, a second transistor in parallel with said first transistor and in series with an impedance coupling said word line to said voltage source, means for turning on said first transistor to set a first selected voltage level on said word line; and means for turning off said first transistor and turning on said second transistor to set a second selected voltage level on said word line; and means for applying a write current to said cell from one of said bit lines while said second transistor is turned on to set one of said cross coupled transistors in a conductive state.
References Cited (Backward Citations)
US3949385A
Cited
US3953839A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-09 | 1980-11-08 | 1981-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-09 | 1984-11-08 | 1985-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-09 | 1988-11-08 | 1989-05-10 | $7700.00 | Window Closed / Lapsed |