US4272832A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1979-05-23
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Granted: 1981-06-09
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Expires: 1999-05-23
Abstract
Abstract A semiconductor memory device comprises an input address buffer circuit and a memory cell circuit which are constructed of static logic circuits, an address decoder circuit which is constructed of a dynamic logic circuit, a detector circuit which detects a change in an input address signal, and a pulse generator circuit which is started operating by an output signal of the detector circuit and which provides a clock signal for the dynamic logic circuit. Owing to the detector circuit and the pulse generator circuit, the semiconductor memory device operates without the necessity for any external clock signal.
Inventors
- 👤 Tsuneo Ito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 07:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
78 words
A semiconductor memory device comprising an input address buffer circuit and a memory cell circuit which are constructed of static logic circuits, an address decoder circuit which is constructed of a dynamic logic circuit, a detector circuit which detects a change in an output signal of said address buffer circuit, and a pulse generator circuit which is started operating by an output signal of said detector circuit and which provides a clock signal for said address decoder circuit.
Claim 2
Dependent Claim
78 words
A semiconductor memory device comprising an input address buffer circuit and a memory cell circuit which are constructed of static logic circuits, an address decoder circuit which is constructed of a dynamic logic circuit, a detector circuit which detects a change in an output signal of said address buffer circuit, and a pulse generator circuit which is started operating by an output signal of said detector circuit and which provides a clock signal for said address decoder circuit.
Claim 3
Dependent Claim
38 words
A semiconductor memory device according to claim 1, wherein said detector circuit is constructed so as to detect a delay time of an output signal of said input address buffer circuit relative to an input address signal thereof.
Claim 4
Dependent Claim
47 words
A semiconductor memory device according to claim 1, wherein said address decoder circuit is constructed so as to start a precharge operation upon a rise of said clock signal and to provide an output signal corresponding to an input signal upon a fall of said clock signal.
Claim 5
Dependent Claim
16 words
A semiconductor memory device as in claim 1, wherein said input address buffer circuit is unclocked.
Claim 6
Dependent Claim
119 words
A semiconductor memory device comprising an input address buffer circuit and a memory cell circuit which are constructed of static logic circuits, an address decoder circuit which is constructed of a dynamic logic circuit, a detector circuit which detects a change in an input address signal, and a pulse generator circuit which is started operating by an output signal of said detector circuit and which provides a clock signal for said dynamic logic circuit, wherein said pulse generator circuit comprises a flip-flop circuit and a signal delay circuit, and said flip-flop circuit is constructed so as to be set by said output signal of said detector circuit and to be reset by an output signal of said delay circuit.
Claim 7
Dependent Claim
119 words
A semiconductor memory device comprising an input address buffer circuit and a memory cell circuit which are constructed of static logic circuits, an address decoder circuit which is constructed of a dynamic logic circuit, a detector circuit which detects a change in an input address signal, and a pulse generator circuit which is started operating by an output signal of said detector circuit and which provides a clock signal for said dynamic logic circuit, wherein said pulse generator circuit comprises a flip-flop circuit and a signal delay circuit, and said flip-flop circuit is constructed so as to be set by said output signal of said detector circuit and to be reset by an output signal of said delay circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-06-08 | 1984-12-08 | 1985-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-06-08 | 1988-12-08 | 1989-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-06-08 | 1992-12-08 | 1993-06-09 | $7700.00 | Window Closed / Lapsed |