Processor bus access

Claim 2

A processor which includes a central processing unit (CPU), a local memory and a local input/output (I/O) device which are coupled to an internal bus, and an input/output (I/O) interface adapted to couple the internal bus to a system bus, the I/O device being adapted to access at least the internal memory through the internal bus, comprising first means for generating a system bus use request (SBUR) signal to an external of the processor on the basis of the address signal outputted from said CPU, and second means operative to put said CPU in a HOLD condition until a system bus use acknowledgment (SBUA) signal is received from the external of the processor.

Claim 3

A processor as set forth in Claim 1 wherein said CPU includes at least a CPU internal bus, a timing controller, a group of registers coupled to said CPU internal bus, and an address buffer coupled to said register group and adapted to supply the address signal to said internal bus of the processor, and wherein said first means is a system bus access controller which includes an address table storing an address discrimination information for discriminating whether an external address is or not, and a comparator adapted to compare said address in said address buffer with the address discrimination information in said address table and to output said system bus use request (SBUR) signal to said system bus, and said second means includes a gate means in response to said SBUR signal to output a HOLD signal to said timing controller thereby putting said CPU in said HOLD condition.

Claim 4

A processor as set forth in Claim 2 wherein said system bus access controller further includes a buffer register having an input coupled to the output of said comparator and an output coupled to said system bus thereby to supplying said SBUR signal directly to said system bus.

Claim 5

A processor as set forth in Claim 2 wherein said gate means is an AND gate having a non-inverted input coupled to the output of said comparator and an inverted input adapted to receive said system bus use acknowledgment (SBUA) signal from said system bus.

Claim 6

A processor as set forth in Claim 4 wherein said CPU is such that when said system bus use acknowledgment (SBUA) signal is inputted to said AND gate to cause said HOLD signal to disappears, said CPU again starts its operation so as to supply at least the address signal stored in said address buffer just before said CPU becomes the HOLD condition, and a control signal through said internal bus of said processor to said I/O interface.

Claim 7

A processor as set forth in Claim 5 wherein said I/O interface includes a bus buffer coupled between said internal bus of said processor and said system bus, a decoder having an input coupled to said internal bus of said processor for receiving at least a portion of said address signal and said control signal supplied from said CPU so as to supply a trigger signal to said bus buffer, and a second gate means in response to said trigger signal to generate and supply a WAIT signal to said CPU through said internal bus of said processor.

Claim 8

A processor as set forth in Claim 6 wherein said second gate means is an AND gate having a non-inverted input coupled to the output of said decoder and an inverted input adapted to receive an access completion signal so that after the access to the external is completed said CPU is released from the WAIT condition.

Claim 9

A processor having a central processing unit (CPU), an internal memory, an internal memory access means, an internal bus coupled to said CPU, said internal memory and said internal memory access means, and means for communicatively coupling said CPU to an external bus, comprising first means generating a request signal for requiring usage of said external bus, second means receiving an acknowledgment signal for designating grant of usage of said system bus, and third means for releasing said internal bus from said CPU during the period of time from the moment said request signal is generated until said acknowledgment signal is received.

Claim 10

A processor having a central processing unit (CPU), an internal memory, an internal memory access means, an internal bus coupled to said CPU, said internal memory and said internal memory access means, and means for communicatively coupling said CPU to an external bus, comprising first means generating a request signal for requiring usage of said external bus, second means receiving an acknowledgment signal for designating grant of usage of said system bus, and third means for releasing said internal bus from said CPU during the period of time from the moment said request signal is generated until said acknowledgment signal is received.

Claim 11

A processor as set forth in Claim 8, wherein said internal memory access means performs an access of said internal memory during said period of time.