Low active-power address buffer

Claim 2

An input buffer circuit for low-power operation comprising: controlled isolation means having a first input terminal for receiving a data signal, a second input terminal for receiving a first control signal and an isolation output terminal, and further having an active power-drawing state and a normal inactive state; latch means having an input terminal, an output terminal, and a control terminal, the input terminal being supplied by the voltage on said isolation output terminal, the output terminal storing the voltage level on said isolation output terminal, and the control terminal being supplied by a second control signal from a latch enable node supplied by the first control signal after a predetermined delay; time control means having a time control output connected to said second input terminal, and having an enabling input terminal for receiving an enabling signal and a timing terminal for receiving a disabling signal, for controlling the duration of said first control signal; and delay means having a delay input terminal connected to said enabling input terminal and a delay output terminal connected to said latch enable node, for enabling said latch a predetermined time after a signal is received on said enabling input terminal; so that, in operation, said controlled isolation means switches to said active power-drawing state in response to an enabling signal for a time duration determined by said delay means, that is not controlled by the duration of said data signal.

Claim 3

An input buffer circuit according to claim 1, in which said controlled isolation means includes a path from a power supply node to ground through at least one transistor controlled by said time control means and through at least two transistors controlled by said data signal, the relative impedances of said transistors on said path being selected so that a pull-down transistor connected between ground and said isolation output terminal and being controlled by said time control means will maintain the voltage on the isolation output terminal within the range corresponding to a logic 1 signal when said transistors connected in series between said isolation output node and said power supply node and being controlled by said data signal means are each conductive.

Claim 4

A buffer circuit comprising an NOR circuit, having a pair of input terminals, one of which is connected to an input data signal terminal, and an output terminal, a NAND circuit having a pair of input terminals, one of which is connected to an enabling input terminal, and an output terminal which is connected to the other input terminal of the NOR circuit, a delay means which includes an output terminal and an input terminal which is connected to said enabling input terminal, first and second complementary pass transistor pairs, the first pair having an input terminal connected to the output terminal of the NOR circuit, an output terminal, and a pair of control terminals, one of which is connected to the output terminal of the delay means, and the other to the output terminal of an inverter whose input terminal is connected to the output terminal of the delay means and to the other terminal of said NAND circuit, the second pair having an input terminal connected to the output terminal of the first pair, an output terminal, and a pair of control terminals, one of which is connected to the output terminal of the delay means and the other of which is connected to the output terminal of said inverter, and latch means comprising a pair of cross coupled inverters, the input terminal of the first inverter being connected to the output terminal of the first complementary pass transistor pair and the output terminal of which is connected to the input terminal of the second inverter, the output terminal of which is connected to the other control terminal of the second complementary pass transistor pair.

Claim 5

A buffer circuit comprising an NOR circuit, having a pair of input terminals, one of which is connected to an input data signal terminal, and an output terminal, a NAND circuit having a pair of input terminals, one of which is connected to an enabling input terminal, and an output terminal which is connected to the other input terminal of the NOR circuit, a delay means which includes an output terminal and an input terminal which is connected to said enabling input terminal, first and second complementary pass transistor pairs, the first pair having an input terminal connected to the output terminal of the NOR circuit, an output terminal, and a pair of control terminals, one of which is connected to the output terminal of the delay means, and the other to the output terminal of an inverter whose input terminal is connected to the output terminal of the delay means and to the other terminal of said NAND circuit, the second pair having an input terminal connected to the output terminal of the first pair, an output terminal, and a pair of control terminals, one of which is connected to the output terminal of the delay means and the other of which is connected to the output terminal of said inverter, and latch means comprising a pair of cross coupled inverters, the input terminal of the first inverter being connected to the output terminal of the first complementary pass transistor pair and the output terminal of which is connected to the input terminal of the second inverter, the output terminal of which is connected to the other control terminal of the second complementary pass transistor pair.