Semiconductor memory device

Claim 2

A semiconductor memory device of a dynamic type comprising a memory cell and a column circuit, operatively connected to said memory cell and operatively connectable to receive column driving signals, said column circuit including a read/write circuit for reading data from or writing data into said memory cell in response to the column driving signals, said read/write circuit comprising: a common input/output terminal for inputting write data into or for outputting read data from said memory cell; a data output buffer, operatively connected to said common input/output terminal, for receiving said read data from said memory cell and for generating control signals; a three-state circuit, operatively connected to said common input/output terminal and to said data output buffer, for receiving said control signals and for generating and applying a first level signal or a second level signal or applying a high impedance to said common input/output terminal according to said control signals; and a data write-in buffer having a latching function and operatively connected between said common input/output terminal and said memory cell; said column circuit further comprising: first means, operatively connected to said data output buffer and operatively connectable to receive said column driving signals, for generating an output disable signal and for causing said data output buffer to generate a high impedance control signal for causing said three-state circuit to apply the high impedance state, in response to one of said column driving signals; and second means, operatively connected to said common input/output terminal and to said data write-in buffer, for latching said write data applied to said common input/output terminal into said data write-in buffer after said three-state circuit has applied said high impedance state, in response to another one of said column driving signals.

Claim 3

A semiconductor memory device as claimed in claim 1, wherein said data write-in buffer is a dynamic circuit comprising: a bistable circuit, operatively connected to said common input/output terminal, for latching said write data; and a write-in circuit, operatively connected to said bistable circuit and to said memory cell, for writing the latched-write data into said memory cell.

Claim 4

A semiconductor memory device as claimed in claim 1 or 2, wherein in said read/write circuit further comprises a write enable state; wherein said data write-in buffer further comprises an enable state; wherein said column driving signals comprise a write enable signal for setting said read/write circuit to the write enable state when said write enable signal is turned on; wherein said first means comprises a latching circuit, operatively connected to said data output buffer, for providing a latched driving signal, in response to a turning on of said write enable signal, wherein said latched driving signal being used to cause said three-state circuit to apply the high impedance even after said write enable signal is turned off; and wherein said second means comprises a gate circuit, operatively connected to said latching circuit and to said data write-in buffer, having a first input for receiving said latched driving signal and having a second input for receiving said write enable signal, said gate circuit for generating a data write-in buffer-driving signal for setting said data write-in buffer to an enable state so as to latch said write data, in response to the turning off of said write enable signal.

Claim 5

A semiconductor memory device as claimed in claim 1 or 2, wherein said data output buffer further comprises a write enable state; wherein said column driving signals comprise a write enable signal and a column-address strobe signal, said column address strobe signal being used to set said data output buffer to the write enable state when said column-address strobe signal is turned off, said first means causing said common input/output terminal to remain at a high impedance when said column-address strobe signal is turned off; and wherein said second means comprises: a latching circuit, operatively connected to receive said column-address strobe signal, for generating a latched signal for keeping said column-address strobe signal ON even after said column-address strobe signal is turned off; and a write-enable buffer, operatively connected to said latching circuit and to said data write-in buffer, for generating a driving signal which is inputted into said data write-in buffer, said driving signal being generated when both said write-enable signal and said latched signal are applied to said write-enable buffer, said data write-in buffer latching said write data when said data write-in buffer receives said driving signal.

Claim 6

A semiconductor memory device, operatively connectable to receive write data, a row address strobe signal, a column address strobe signal and a write enable signal, comprising: a memory cell for storing the write data and for generating read data; a row enable buffer, operatively connectable to receive the row address strobe signal, for generating a row enable signal in dependence upon the row address strobe signal; a column enable buffer, operatively connected to said row enable buffer and operatively connectable to receive the column address strobe signal, for generating a column enable signal in dependence upon the row enable signal and the column address strobe signal; an output disable buffer, operatively connected to said column enable buffer and operatively connectable to receive the write enable signal, for generating an output disable signal in dependence upon the column enable signal and the write enable signal; an AND gate, operatively connected to said output disable buffer and operatively connectable to receive the write enable signal, for generating an output signal in dependence upon the write enable signal and the output disable signal; a write enable buffer, operatively connected to said column enable buffer and said AND gate, for generating a driving signal in dependence upon the column enable signal and the output signal; a data output buffer, operatively connected to said output disable buffer, said column enable buffer and said memory cell, for generating control signals in dependence upon the output disable signal, the column disable signal and the read data; a three-state circuit, operatively connected to said data output buffer, for generating output data or applying a first impedance level in dependence upon the control signals; an input/output terminal, operatively connected to said three-state circuit and operatively connectable to receive the write data, for passing therethrough the write data and the output data; and a dynamic data write-in buffer, operatively connected to said input/output terminal, said column enable buffer, said write enable buffer and said memory cell, for passing therethrough the write data in dependence upon the column enable signal and the driving signal, so that when the write data is passed through said dynamic data write-in buffer said three-state circuit applies the first impedance level.

Claim 7

A semiconductor memory device, operatively connectable to receive write data, a row address strobe signal, a column address strobe signal and a write enable signal, comprising: a memory cell for storing the write data and for generating read data; a row enable buffer, operatively connectable to receive the row address strobe signal, for generating a row enable signal in dependence upon the row address strobe signal; a column enable buffer, operatively connected to said row enable buffer and operatively connectable to receive the column address strobe signal, for generating a column enable signal in dependence upon the row enable signal and the column address strobe signal; an output disable buffer, operatively connected to said column enable buffer and operatively connectable to receive the write enable signal, for generating an output disable signal in dependence upon the column enable signal and the write enable signal; an AND gate, operatively connected to said output disable buffer and operatively connectable to receive the write enable signal, for generating an output signal in dependence upon the write enable signal and the output disable signal; a write enable buffer, operatively connected to said column enable buffer and said AND gate, for generating a driving signal in dependence upon the column enable signal and the output signal; a data output buffer, operatively connected to said output disable buffer, said column enable buffer and said memory cell, for generating control signals in dependence upon the output disable signal, the column disable signal and the read data; a three-state circuit, operatively connected to said data output buffer, for generating output data or applying a first impedance level in dependence upon the control signals; an input/output terminal, operatively connected to said three-state circuit and operatively connectable to receive the write data, for passing therethrough the write data and the output data; and a dynamic data write-in buffer, operatively connected to said input/output terminal, said column enable buffer, said write enable buffer and said memory cell, for passing therethrough the write data in dependence upon the column enable signal and the driving signal, so that when the write data is passed through said dynamic data write-in buffer said three-state circuit applies the first impedance level.

Claim 8

A semiconductor memory device as claimed in claim 5, wherein said dynamic write-in circuit comprises: a bistable circuit, operatively connected to said input/output terminal, said column enable buffer and said write enable buffer, for latching the write data in dependence upon the column enable signal and the driving signal; and a write-in circuit, operatively connected to said bistable circuit, said write enable buffer and said memory cell, for writing the latched write data into said memory cell in dependence upon the driving signal.

Claim 9

A semiconductor memory device, operatively connectable to receive write data, a row address strobe signal, a column address strobe signal and a write enable signal, comprising: a memory cell for storing the write data and for generating read data; a row enable buffer, operatively connectable to receive the row address strobe signal, for generating a row enable signal in dependence upon the row address strobe signal; a column enable buffer, operatively connected to said row enable buffer and operatively connectable to receive the column address strobe signal, for generating a column enable signal in dependence upon the row enable signal and the column address strobe signal; a latching circuit, operatively connected to said column enable buffer and said row enable buffer, for generating a latched column enable signal in dependence upon the column enable signal and the row enable signal; a write enable buffer, operatively connected to said latching circuit and to said row enable buffer and operatively connectable to receive the write enable signal, for generating a driving signal in dependence upon the latched column enable signal, the row enable signal and the write enable signal; a data output buffer, operatively connected to said column enable buffer, said row enable buffer and said memory cell, for generating control signals in dependence upon the column enable signal, the row enable signal and the read data; a three-state circuit, operatively connected to said data output buffer, for generating output data or applying a first impedance level in dependence upon the control signals; an input/output terminal, operatively connected to said three-state circuit and operatively connectable to receive the write data, for passing therethrough the write data and the output data; and a dynamic data write-in buffer, operatively connected to said input/output terminal, said write enable buffer, said row enable buffer and said memory cell, for passing therethrough the write data in dependence upon the row enable signal and the driving signal, so that when said write data is passed through said dynamic data write-in buffer said three-state circuit applies the first impedance level.

Claim 10

A semiconductor memory device, operatively connectable to receive write data, a row address strobe signal, a column address strobe signal and a write enable signal, comprising: a memory cell for storing the write data and for generating read data; a row enable buffer, operatively connectable to receive the row address strobe signal, for generating a row enable signal in dependence upon the row address strobe signal; a column enable buffer, operatively connected to said row enable buffer and operatively connectable to receive the column address strobe signal, for generating a column enable signal in dependence upon the row enable signal and the column address strobe signal; a latching circuit, operatively connected to said column enable buffer and said row enable buffer, for generating a latched column enable signal in dependence upon the column enable signal and the row enable signal; a write enable buffer, operatively connected to said latching circuit and to said row enable buffer and operatively connectable to receive the write enable signal, for generating a driving signal in dependence upon the latched column enable signal, the row enable signal and the write enable signal; a data output buffer, operatively connected to said column enable buffer, said row enable buffer and said memory cell, for generating control signals in dependence upon the column enable signal, the row enable signal and the read data; a three-state circuit, operatively connected to said data output buffer, for generating output data or applying a first impedance level in dependence upon the control signals; an input/output terminal, operatively connected to said three-state circuit and operatively connectable to receive the write data, for passing therethrough the write data and the output data; and a dynamic data write-in buffer, operatively connected to said input/output terminal, said write enable buffer, said row enable buffer and said memory cell, for passing therethrough the write data in dependence upon the row enable signal and the driving signal, so that when said write data is passed through said dynamic data write-in buffer said three-state circuit applies the first impedance level.

Claim 11

A semiconductor memory device as claimed in claim 7, wherein said dynamic write-in circuit comprises: a bistable circuit operatively connected to said input/output terminal, said row enable buffer and said write enable buffer, for latching the write data in dependence upon the row enable signal and the driving signal; and a write-in circuit, operatively connected to said bistable circuit, said write enable buffer and said memory cell, for writing the latched write data into said memory cell in dependence upon the driving signal.